LECTURE No. 17. Command structures in Assembler

1. Machine instruction structure

A machine command is an instruction to the microprocessor encoded according to certain rules to perform some operation or action. Each command contains elements that define:

1) what to do? (The answer to this question is given by the command element called the operation code (COP).);

2) objects on which something needs to be done (these elements are called operands);

3) how to do? (These elements are called operand types and are usually implicit.)

The machine instruction format shown in Figure 20 is the most general. The maximum length of a machine instruction is 15 bytes. A real command may contain a much smaller number of fields, up to one - only COP.

Rice. 20. Machine instruction format

Let us describe the purpose of the machine instruction fields.

1. Prefixes.

Optional machine instruction elements, each of which is 1 byte or may be omitted. In memory, prefixes precede the command. The purpose of prefixes is to modify the operation performed by the command. An application can use the following types of prefixes:

1) segment replacement prefix. Explicitly specifies which segment register is used in this instruction to address the stack or data. The prefix overrides the default segment register selection. Segment replacement prefixes have the following meanings:

a) 2eh - replacement of segment cs;

b) 36h - replacement of segment ss;

c) 3eh - replacement of segment ds;

d) 26h - replacement of segment es;

e) 64h - replacement of segment fs;

e) 65h - replacement of segment gs;

2) the address bitness prefix specifies the bitness of the address (32- or 16-bit). Each instruction that uses an address operand is assigned the bit width of that operand's address. This address can be 16 or 32 bits. If the address length for this command is 16 bits, this means that the command contains a 16-bit offset (Fig. 20), it corresponds to a 16-bit offset of the address operand relative to the beginning of some segment. In the context of Figure 21, this offset is called the effective address. If the address is 32 bits, this means that the command contains a 32-bit offset (Fig. 20), it corresponds to a 32-bit offset of the address operand relative to the beginning of the segment, and its value forms a 32-bit offset in the segment. With the address bitness prefix, you can change the default address bitness. This change will only affect the command preceded by the prefix;

Rice. 21. The mechanism of formation of a physical address in real mode

3) Operand bit width prefix is ​​similar to address bit width prefix, but indicates the operand bit length (32-bit or 16-bit) with which the instruction operates. What are the rules for setting address and operand bit width attributes by default?

In real mode and virtual 18086 mode, the values ​​of these attributes are 16 bits. In protected mode, the attribute values ​​depend on the state of the D bit in the executable segment descriptors. If D = 0, then default attribute values ​​are 16 bits; if D = 1, then 32 bits.

Prefix values ​​for operand width 66h and address width 67h. With the real mode address bit prefix, you can use 32-bit addressing, but be aware of the 64 KB segment size limit. Similar to the address-width prefix, you can use the real-mode operand-width prefix to work with 32-bit operands (for example, in arithmetic instructions);

4) the repetition prefix is ​​used with chain commands (line processing commands). This prefix "loops" the command to process all elements of the chain. The command system supports two types of prefixes:

a) unconditional (rep - OOh), forcing the chained command to be repeated a certain number of times;

b) conditional (repe/repz - OOh, repne/repnz - 0f2h), which, when looping, check some flags, and as a result of the check, early exit from the loop is possible.

2. Operation code.

Required element that describes the operation performed by the command. Many commands correspond to several operation codes, each of which determines the nuances of the operation. The subsequent fields of the machine instruction determine the location of the operands involved in the operation and the specifics of their use. Consideration of these fields is connected with the ways of specifying operands in a machine instruction and therefore will be performed later.

3. Addressing mode byte modr/m.

The value of this byte determines the operand address form used. Operands can be in memory in one or two registers. If the operand is in memory, then the modr/m byte specifies the components (offset, base and index registers) used to calculate its effective address (Figure 21). In protected mode, the sib byte (Scale-Index-Base) can additionally be used to determine the location of the operand in memory. The modr/m byte consists of three fields (Fig. 20):

1) the mod field determines the number of bytes occupied by the operand address in the command (Fig. 20, the offset field in the command). The mod field is used in conjunction with the r/m field, which specifies how to modify the address of the "instruction offset" operand. For example, if mod = 00, this means that there is no offset field in the command, and the address of the operand is determined by the contents of the base and (or) index register. Which registers will be used to calculate the effective address is determined by the value of this byte. If mod = 01, this means that the offset field is present in the command, occupies 1 byte and is modified by the contents of the base and (or) index register. If mod = 10, this means that the offset field is present in the command, occupies 2 or 4 bytes (depending on the default or prefix-defined address size), and is modified by the contents of the base and/or index register. If mod = 11, this means that there are no operands in memory: they are in registers. The same value of the mod byte is used when an immediate operand is used in the instruction;

2) the reg/cop field determines either the register located in the command in place of the first operand, or a possible extension of the opcode;

3) the r/m field is used in conjunction with the mod field and determines either the register located in the command at the place of the first operand (if mod = 11), or the base and index registers used to calculate the effective address (together with the offset field in the command).

4. Byte scale - index - base (byte sib).

Used to expand the possibilities of addressing operands. The presence of the sib byte in a machine instruction is indicated by a combination of one of the values ​​01 or 10 of the mod field and the value of the r/m = 100 field. The sib byte consists of three fields:

1) scale fields ss. This field contains the scaling factor for the index component index, which occupies the next 3 bits of the sib byte. The ss field can contain one of the following values: 1, 2, 4, 8.

When calculating the effective address, the contents of the index register will be multiplied by this value;

2) index fields. Used to store the index register number that is used to calculate the effective address of the operand;

3) base fields. Used to store the base register number, which is also used to calculate the effective address of the operand. Almost all general purpose registers can be used as base and index registers.

5. Offset field in command.

An 8-, 16-, or 32-bit signed integer representing, in whole or in part (subject to the above considerations), the value of the effective address of the operand.

6. The field of the immediate operand.

An optional field that is an 8-bit, 16-bit, or 32-bit immediate operand. The presence of this field is, of course, reflected in the value of the modr/m byte.

2. Methods for specifying instruction operands

The operand is set implicitly at the firmware level

In this case, the instruction explicitly contains no operands. The command execution algorithm uses some default objects (registers, flags in eflags, etc.).

For example, the cli and sti commands implicitly work with the if interrupt flag in the eflags register, and the xlat command implicitly accesses the al register and a line in memory at the address specified by the ds:bx register pair.

The operand is specified in the instruction itself (immediate operand)

The operand is in the instruction code, that is, it is part of it. To store such an operand in a command, a field up to 32 bits long is allocated (Figure 20). The immediate operand can only be the second (source) operand. The destination operand can be either in memory or in a register.

For example: mov ax,0ffffti moves the hexadecimal constant ffff into register ax. The add sum, 2 command adds the contents of the field at the address sum with the integer 2 and writes the result at the place of the first operand, i.e. into memory.

The operand is in one of the registers

Register operands are specified by register names. Registers can be used:

1) 32-bit registers EAX, EBX, ECX, EDX, ESI, EDI, ESP, EUR;

2) 16-bit registers AX, BX, CX, DX, SI, DI, SP, BP;

3) 8-bit registers AH, AL, BH, BL, CH, CL, DH, DL;

4) segment registers CS, DS, SS, ES, FS, GS.

For example, the add ax,bx instruction adds the contents of registers ax and bx and writes the result to bx. The dec si command decrements the contents of si by 1.

The operand is in memory

This is the most complex and at the same time the most flexible way to specify operands. It allows you to implement the following two main types of addressing: direct and indirect.

In turn, indirect addressing has the following varieties:

1) indirect base addressing; its other name is register indirect addressing;

2) indirect base addressing with offset;

3) indirect index addressing with offset;

4) indirect base index addressing;

5) indirect base index addressing with offset.

The operand is an I/O port

In addition to the RAM address space, the microprocessor maintains an I/O address space, which is used to access I/O devices. The I/O address space is 64 KB. Addresses are allocated for any computer device in this space. A particular address value within this space is called an I/O port. Physically, the I / O port corresponds to a hardware register (not to be confused with a microprocessor register), which is accessed using special assembler instructions in and out.

For example:

in al,60h; enter a byte from port 60h

Registers addressed by an I/O port can be 8,16, 32, or XNUMX bits wide, but the register bit width is fixed for a particular port. The in and out commands operate on a fixed range of objects. The so-called accumulator registers EAX, AX, AL are used as a source of information or a recipient. The choice of register is determined by the bitness of the port. The port number can be specified as an immediate operand in the in and out instructions, or as a value in the DX register. The last method allows you to dynamically determine the port number in the program.

The operand is on the stack

Instructions may have no operands at all, may have one or two operands. Most instructions require two operands, one of which is the source operand and the other is the destination operand. It is important that one operand can be located in a register or memory, and the second operand must be in a register or directly in the instruction. An immediate operand can only be a source operand. In a two-operand machine instruction, the following combinations of operands are possible:

1) register - register;

2) register - memory;

3) memory - register;

4) immediate operand - register;

5) immediate operand - memory.

There are exceptions to this rule regarding:

1) chain commands that can move data from memory to memory;

2) stack commands that can transfer data from memory to a stack that is also in memory;

3) commands of the multiplication type, which, in addition to the operand specified in the command, also use a second, implicit operand.

Of the listed combinations of operands, register - memory and memory - register are most often used. In view of their importance, we will consider them in more detail. We will accompany the discussion with examples of assembler instructions that will show how the format of an assembler instruction changes when one or another type of addressing is applied. In this regard, look again at Figure 21, which shows the principle of forming a physical address on the address bus of the microprocessor. It can be seen that the address of the operand is formed as the sum of two components - the contents of the segment register shifted by 4 bits and the 16-bit effective address, which is generally calculated as the sum of three components: base, offset and index.

3. Addressing methods

We list and then consider the features of the main types of addressing operands in memory:

1) direct addressing;

2) indirect basic (register) addressing;

3) indirect basic (register) addressing with offset;

4) indirect index addressing with offset;

5) indirect base index addressing;

6) indirect base index addressing with offset.

Direct Addressing

This is the simplest form of addressing an operand in memory, since the effective address is contained in the instruction itself and no additional sources or registers are used to form it. The effective address is taken directly from the machine instruction offset field (see Figure 20), which can be 8, 16, 32 bits in size. This value uniquely identifies the byte, word, or double word located in the data segment.

Direct addressing can be of two types.

Relative direct addressing

Used for conditional jump instructions to indicate the relative jump address. The relativity of such a transition lies in the fact that the offset field of the machine instruction contains an 8-, 16- or 32-bit value, which, as a result of the operation of the instruction, will be added to the contents of the ip/eip instruction pointer register. As a result of this addition, the address is obtained, to which the transition is carried out.

Absolute direct addressing

In this case, the effective address is part of the machine instruction, but this address is formed only from the value of the offset field in the instruction. To form the physical address of the operand in memory, the microprocessor adds this field with the value of the segment register shifted by 4 bits. Several forms of this addressing can be used in an assembler instruction.

But such addressing is rarely used - commonly used cells in the program are assigned symbolic names. During translation, the assembler calculates and substitutes the offset values ​​of these names into the machine instruction it generates in the "instruction offset" field. As a result, it turns out that the machine instruction directly addresses its operand, having, in fact, in one of its fields the value of the effective address.

Other types of addressing are indirect. The word "indirect" in the name of these types of addressing means that only a part of the effective address can be in the instruction itself, and its remaining components are in registers, which are indicated by their contents by the modr/m byte and, possibly, by the sib byte.

Indirect basic (register) addressing

With this addressing, the effective address of the operand can be in any of the general purpose registers, except for sp / esp and bp / ebp (these are specific registers for working with a stack segment). Syntactically, in a command, this addressing mode is expressed by enclosing the register name in square brackets []. For example, the instruction mov ax, [ecx] places in registers ax the contents of the word at the address from the data segment with the offset stored in register esx. Since the contents of the register can be easily changed during the course of the program, this addressing method allows you to dynamically assign the address of an operand for some machine instruction. This property is very useful, for example, for organizing cyclic calculations and for working with various data structures such as tables or arrays.

Indirect base (register) addressing with offset

This type of addressing is an addition to the previous one and is designed to access data with a known offset relative to some base address. This type of addressing is convenient to use to access the elements of data structures, when the offset of the elements is known in advance, at the stage of program development, and the base (starting) address of the structure must be calculated dynamically, at the stage of program execution. Modification of the contents of the base register allows you to access the elements of the same name in different instances of the same type of data structures.

For example, the instruction mov ax,[edx+3h] transfers the words from the memory area to the registers ax at the address: the contents of edx + 3h.

The mov ax,mas[dx] instruction moves a word into register ax at the address: the contents of dx plus the value of the identifier mas (remember that the compiler assigns to each identifier a value equal to the offset of this identifier from the beginning of the data segment).

Indirect index addressing with offset

This kind of addressing is very similar to indirect base addressing with an offset. Here, too, one of the general purpose registers is used to form the effective address. But index addressing has one interesting feature that is very convenient for working with arrays. It is connected with the possibility of the so-called scaling of the contents of the index register. What it is?

Look at Figure 20. We are interested in the sib byte. When discussing the structure of this byte, we noted that it consists of three fields. One of these fields is the ss scale field, by which the contents of the index register are multiplied.

For example, in the mov ax,mas[si*2] instruction, the value of the effective address of the second operand is calculated by the expression mas+(si)*2. Due to the fact that the assembler does not have the means to organize array indexing, the programmer has to organize it on his own.

The ability to scale significantly helps in solving this problem, but provided that the size of the array elements is 1, 2, 4 or 8 bytes.

Indirect base index addressing

With this type of addressing, the effective address is formed as the sum of the contents of two general-purpose registers: base and index. These registers can be any general-purpose registers, and scaling of the contents of an index register is often used.

Indirect base index addressing with offset

This kind of addressing is the complement of indirect indexed addressing. The effective address is formed as the sum of three components: the contents of the base register, the contents of the index register, and the value of the offset field in the command.

For example, the mov eax,[esi+5] [edx] instruction moves a double word to the eax register at the address: (esi) + 5 + (edx).

The add ax,array[esi] [ebx] command adds the contents of register ax to the contents of the word at the address: the value of the identifier array + (esi) + (ebx).

Author: Tsvetkova A.V.

<< Back: Assembly Instruction Structures (Structure of a machine instruction. Methods for specifying instruction operands. Addressing methods)

>> Forward: Control Transfer Commands (Logical commands. Truth table for logical negation. Truth table for logical inclusive OR. Truth table for logical AND. Truth table for logical exclusive OR. Meaning of abbreviations in the jcc command name. List of conditional jump commands for the command. Conditional jump commands and flags)

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