LECTURE No. 15. Registers

1. Microprocessor system registers

The very name of these registers suggests that they perform specific functions in the system. The use of system registers is strictly regulated. It is they who provide the protected mode. They can also be thought of as part of the microprocessor architecture, which is deliberately left visible so that a qualified system programmer can perform the most low-level operations.

System registers can be divided into three groups:

1) four control registers;

2) four registers of system addresses;

3) eight debug registers.

2. Control registers

The group of control registers includes four registers: cr0, cr1, cr2, cr3. These registers are for general system control. Control registers are only available to programs with privilege level 0.

Although the microprocessor has four control registers, only three of them are available - cr1 is excluded, the functions of which are not yet defined (it is reserved for future use).

The cr0 register contains system flags that control the modes of operation of the microprocessor and reflect its state globally, regardless of the specific tasks being performed.

Purpose of system flags:

1) pe (Protect Enable), bit 0 - enable the protected mode of operation. The state of this flag shows in which of the two modes - real (pe = 0) or protected (pe = 1) - the microprocessor is operating at a given time;

2) mp (Math Present), bit 1 - the presence of a coprocessor. Always 1;

3) ts (Task Switched), bit 3 - task switching. The processor automatically sets this bit when it switches to another task;

4) am (Alignment Mask), bit 18 - alignment mask. This bit enables (am = 1) or disables (am = 0) alignment control;

5) cd (Cache Disable), bit 30 - disable cache memory.

Using this bit, you can disable (cd =1) or enable (cd = 0) the use of the internal cache (the first level cache);

6) pg (PaGing), bit 31 - enable (pg =1) or disable (pg = 0) paging.

The flag is used in the paging model of memory organization.

The cr2 register is used in RAM paging to register the situation when the current instruction accessed the address contained in a memory page that is currently not in memory.

In such a situation, an exception number 14 occurs in the microprocessor, and the linear 32-bit address of the instruction that caused this exception is written to register cr2. With this information, the exception handler 14 determines the desired page, swaps it into memory and resumes the normal operation of the program;

The cr3 register is also used for paging memory. This is the so-called first-level page directory register. It contains the 20-bit physical base address of the current task's page directory. This directory contains 1024 32-bit descriptors, each of which contains the address of the second level page table. In turn, each of the second level page tables contains 1024 32-bit descriptors that address page frames in memory. The page frame size is 4 KB.

3. Registers of system addresses

These registers are also called memory management registers.

They are designed to protect programs and data in the multitasking mode of the microprocessor. When operating in microprocessor protected mode, the address space is divided into:

1) global - common to all tasks;

2) local - separate for each task.

This separation explains the presence of the following system registers in the microprocessor architecture:

1) the register of the global descriptor table gdtr (Global Descriptor Table Register), having a size of 48 bits and containing a 32-bit (bits 16-47) base address of the global descriptor table GDT and a 16-bit (bits 0-15) limit value, which is size in bytes of the GDT table;

2) the local descriptor table register ldtr (Local Descriptor Table Register), having a size of 16 bits and containing the so-called selector of the descriptor of the local descriptor table LDT This selector is a pointer in the GDT table, which describes the segment containing the local descriptor table LDT;

3) the register of the interrupt descriptor table idtr (Interrupt Descriptor Table Register), having a size of 48 bits and containing a 32-bit (bits 16-47) base address of the IDT interrupt descriptor table and a 16-bit (bits 0-15) limit value, which is size in bytes of the IDT table;

4) 16-bit task register tr (Task Register), which, like the ldtr register, contains a selector, i.e. a pointer to a descriptor in the GDT table. This descriptor describes the current Task Segment Status (TSS). This segment is created for each task in the system, has a strictly regulated structure and contains the context (current state) of the task. The main purpose of TSS segments is to save the current state of a task at the moment of switching to another task.

4. ​​Debug registers

This is a very interesting group of registers intended for hardware debugging. Hardware debugging tools first appeared in the i486 microprocessor. In hardware, the microprocessor contains eight debug registers, but only six of them are actually used.

Registers dr0, dr1, dr2, dr3 have a width of 32 bits and are designed to set the linear addresses of four breakpoints. The mechanism used in this case is the following: any address generated by the current program is compared with the addresses in registers dr0... dr3, and if there is a match, a debugging exception with number 1 is generated.

Register dr6 is called the debug status register. The bits in this register are set according to the reasons that caused the last exception number 1 to occur.

We list these bits and their purpose:

1) b0 - if this bit is set to 1, then the last exception (interrupt) occurred as a result of reaching the checkpoint defined in register dr0;

2) b1 - similar to b0, but for a checkpoint in register dr1;

3) b2 - similar to b0, but for a checkpoint in register dr2;

4) bЗ - similar to b0, but for a checkpoint in register dr3;

5) bd (bit 13) - serves to protect the debug registers;

6) bs (bit 14) - set to 1 if exception 1 was caused by the state of the flag tf = 1 in the eflags register;

7) bt (bit 15) is set to 1 if exception 1 was caused by a switch to a task with the trap bit set in TSS t = 1.

All other bits in this register are filled with zeros. Exception handler 1, based on the contents of dr6, must determine the reason for the exception and take the necessary actions.

Register dr7 is called the debug control register. It contains fields for each of the four debug breakpoint registers that allow you to specify the following conditions under which an interrupt should be generated:

1) checkpoint registration location - only in the current task or in any task. These bits occupy the lower 8 bits of register dr7 (2 bits for each breakpoint (actually a breakpoint) set by registers dr0, dr1, dr2, dr3, respectively).

The first bit of each pair is the so-called local resolution; setting it tells the breakpoint to take effect if it is within the current task's address space.

The second bit in each pair specifies the global permission, which indicates that the given breakpoint is valid within the address spaces of all tasks in the system;

2) the type of access by which the interrupt is initiated: only when fetching a command, when writing, or when writing / reading data. The bits that determine this nature of the occurrence of an interrupt are located in the upper part of this register. Most of the system registers are programmatically accessible.

Author: Tsvetkova A.V.

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