MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data

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MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data

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Encyclopedia of radio electronics and electrical engineering / Application of microcircuits

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Overview

The STA013 is a fully integrated universal decoder for MPEG Layer III Audio streams of the MPEG 1, MPEG 2 and MPEG 2.5 specifications. Here are the main functions of the chip: Full support for the following compressed audio signal formats:

Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) and ISO/IEC 13818-3.2 (MPEG 2 Audio) standards;
low sample rate streams known as MPEG 2.5;
Layer III streams in Stereo, Dual Channel, Single Channel (mono) modes.

In addition, the microcircuit provides and has:

support for all standard sampling rates for MPEG 1 and MPEG 2 plus an extended set of frequencies for MPEG 2.5: 48; 44,1; 32; 24; 22,05; 16; 12; 11,025 and 8 kHz;
MPEG 2.5 Layer III stream support with encoding rates from 8 to 320 kbps;
software control of channel switching in the output signal;
digital control of the output signal level;
digital control of the level of low and high frequencies in the output signal (timbre control);
operation of the serial interface for data;
support for software-controlled data format for the output serial interface (PCM);
low power consumption (85 mW at 2,4 V supply voltage and maximum signal sampling rate);
input data integrity check (CRC) and detection of input stream synchronization errors with the possibility of registering these errors by an external controller.

The microcircuit is controlled via bus I²C.

External quartz resonators with frequencies of 10, 14,31818 and 14,7456 MHz can be connected to the microcircuit (other frequencies can also be supported, but this will require the appropriate version of the internal software (firmware). The main scope of the microcircuit is audio equipment with support for the MP3 format : CD players, MP3 players, music centers Low voltage supply and low power consumption make this chip especially suitable for portable and portable devices. The main characteristics of the microcircuit are given in Table 3.

Table 1

Features	Value
Chip supply voltage, V	2,1 ... 3,6
Dissipated power, mW:\at sampling rate 24kHz\32kHz\48kHz	\76\79\85
Working temperature range, ^oC	-20 ... + 125
Output signal level control range, dB	-96 ... 0
Output level adjustment step, dB	1
Treble level adjustment range, dB	-18 ... + 18
Bass level adjustment range, dB	-18 ... + 18
Frequency level control step (high and low), dB	1,5
Reset signal duration (RESET), µs	however 0,1

The main subsystems of the STA013 chip

The block diagram of the microcircuit is shown in fig. 1. The input serial interface is used to receive an input data stream from an external source. Bit order - the most significant bit of the transmitted bytes is transmitted first. Data is received via the SDI input and is synchronized to the change in signal level at the SCKR input. Synchronization adjustment (reception of data on the edge or fall of the pulse) is carried out programmatically. A low level at the BIT_EN input disables the input interface from receiving data.

MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data. Structural diagram of the STA013 chip
Rice. 1. Structural diagram of the microcircuit

The frequency synthesizer and the synchronization module are used to generate clock signals for the computing core of the microcircuit and for the output audio interface. The output sample rates are obtained by dividing the OCLK resampling rate by a software-defined factor. The frequency synthesizer can generate output signals to drive most of the common DAC chips.

The output serial interface is used to output decoded audio data in PCM format. The data is transmitted over the SDO line and is clocked at the SCKT output. Synchronization adjustment (data transmission on the edge or fall of the pulse) is carried out programmatically. The signal level at the LRCKT output indicates the channel (left/right) for which the data word is being transmitted. The signal representation accuracy can be selected by software from four values: 16, 18, 20 or 24 bits. With a representation precision of 16 bits selected, 32 bits of data are transmitted in one period of the LRCKT signal. If the representation precision is 18, 20, or 24 bits, then 64 data bits are transmitted in one period of the LRCKT signal. The format of the transmitted data is controlled by software, which allows you to connect to the chip many different types of external DACs that support a serial data transfer protocol.

The I2C interface is used to control the operating modes of the microcircuit by means of an external microcontroller, as well as to obtain information about the current state of the microcircuit modules. All adjustment parameters of the microcircuit are recorded in internal registers and are available for writing on the I bus²C. The computing core of the chip is a high-performance digital signal processor (DSP) that provides MP3 audio stream decoding, digital signal filtering, and control of the chip clock module.

Chip operating modes

The STA013 chip can operate in two modes - Multimedia Mode (MM) or Broadcast Mode (hereinafter referred to as BM). In MM mode, the input data stream is controlled by the STA013 chip itself by changing the signal level at the DATA_REQ output. An active signal at this output indicates to an external source that it is necessary to transmit data to the STA013 chip. When operating in this mode, the SRC_INT pin must be connected to a power supply. In BM mode, the input data stream is completely controlled by the data source. In the event of a discrepancy between the real input data rate and the specified nominal rate, the STA013 microcircuit provides the necessary internal synchronization automatically. The BM mode is mainly required for the operation of the chip in wearable or portable devices.

The pinout of the microcircuit for each of the embodiments is shown in fig. 2, and the switching circuit is in fig. 3 and 4.

MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data. STA013 chip pinout
Rice. 2. Pinout of the microcircuit

MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data. Wiring diagram STA013
Rice. 3. Switching scheme

MPEG 2.5 LAYER III STA013/013B/013T audio decoders. Reference data. Wiring diagram STA013
Rice. 4. Switching scheme

The pin assignment of the STA013 chip is given in Table. 2.

Table 2

Pin number			designation	Description
Housing SO8	Enclosure TQFP44	Package LBGA64	designation	Description
1	29	B5	VDD_1	Supply voltage
2	30	B4	VSS_1	common wire
3	31	A4	SDA	Enter exit. Bus data line I²C
4	32	B3	SCL	Entrance. Bus clock I²C
5	34	A1	SDI	Entrance. Serial input data line
6	36	B2	SCKR	Entrance. Serial input clock
7	38	D4	BIT_EN	Entrance. Input Validity Signal
8	40	D1	SRC_INT	Entrance. Interrupt signal from input source
9	42	E2	SDO	Exit. Serial output data line (PCM decoded data)
10	44	F2	SCKT	Exit. Serial Output Clock
11	2	H1	LRCKT	Exit. Channel Data Clock (L/R)
12	3	H3	OCLK	Enter exit. Oversampling clock for external DAC
13	5	F3	VSS_2	common wire
14	6	E4	VDD_2	Supply voltage
15	7	G4	VSS_3	common wire
16	8	G5	VDD_3	Supply voltage
17	10	F5	PVDD	Frequency synthesizer supply voltage
18	11	G6	PVSS	Common wire of the frequency synthesizer
19	12	G7	FILT	Exit. Clock output filter
20	13	G8	XTO	Exit. Connecting a quartz resonator
21	15	F7	XTI	Entrance. Connecting a quartz resonator
22	19	E7	VSS_4	common wire
23	21	C8	VDD_4	Supply voltage
24	22	D7	TRY OUT NOW	Entrance. Enabling test mode
25	24	A7	SCANEN	Sign In
26	25	B6	RESET	Entrance. Hardware reset signal
27	26	A5	VSS_5	common wire
28	27	C5	OUT_CLK/DATA_REQ	Output Buffer Clock/Data Request Signal

Author: Vladimir Zaitsev; Publication: cxem.net

See other articles Section Application of microcircuits.

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