Master generators of switching power supplies. Encyclopedia of radio electronics and electrical engineering

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When designing push-pull pulse voltage converters, it is necessary to take measures to prevent through current through switching transistors. It is possible to ensure the normal operation of the converters if a signal of a special form (other than a meander) is generated to control the transistors.

When designing switching power supplies (UPS) operating at an increased frequency, the main attention is paid to ensuring their reliability and high efficiency. It is these qualities that push-pull UPSs have [1]. However, without taking special measures to eliminate the through current, it is impossible to achieve stable operation of the units with an acceptable efficiency factor (80%).

The through current in push-pull UPSs occurs due to the finite (non-zero) turn-off time of the switching transistors. The fact is that the turn-off time (toff) of most powerful transistors used in the UPS is in the range of 1,5 ... 8 μs, and their turn-on time (ton) is about ten times less. This leads to the fact that at an increased frequency the current shape in the collector circuits is distorted, it becomes different from the meander. As a result, the duration of the current pulses increases and, especially on the decline, their steepness decreases.

On fig. 1 shows the current shape of the base of UPS transistors (diagrams a and b) and their collector (c and d). It can be seen from the diagrams that during the decrease in current IK1, the current IK2 increases, which just leads to the appearance of a through current. In diagrams c and d, the dashed line shows the through current at the fronts and falls of the current pulses of the collectors of switching transistors.

A radical method for eliminating the through current is the formation in master oscillators (CG) of pulses that differ from the meander and have pauses (tp), the duration of which, in the first approximation, is tp = toff - ton. However, in practice, the turn-on and turn-off times are different even for two identical transistors. It depends on the voltage of the primary power source, the temperature of the junctions, the collector current, etc. Therefore, the duration of the pause must be greater than the specified value, and preferably adjustable.

The purpose of this article is to offer the simplest ways to generate pulses in the ZG suitable for UPS control. It contains CG schemes of varying complexity, providing both fixed and adjustable pause duration.

The device, the scheme of which is shown in Fig. 2 allows you to generate a pulse sequence with an adjustable pause. The clock generator is assembled on the elements DD1.1-DD1.3. It generates pulses - a meander of twice the frequency compared to the switching frequency of the switching transistors (Fig. 3, diagram a). The differentiating circuit C2R2 generates short high-level trigger pulses that control the operation of the pause duration generator on the elements DD2.1, DD2.2 (Fig. 3, diagram b).

From the output of the shaper, the pulses are fed to the inputs of the elements DD2.3, DD2.4 and the trigger DD3.1, which act as a pulse distributor. At the outputs of the CG (diagrams e, f), pulse sequences are formed, shifted relative to each other by 180°, with a pause of duration tp. The pulse frequency at the output of the CG is two times less than at the output of the clock generator. The duration of the pause is regulated by a variable resistor R3.

Sometimes it is necessary to receive low-level pulses with a pause to control the UPS. In this case, in the diagram of Fig. 2 elements DD2.1, DD2.2 of the K561LE5 chip are replaced with one element of the K561LS2 chip, and instead of the elements DD2.3, DD2.4, the AND-OR elements are included according to the 2OR circuit. To do this, it is only necessary to apply a high-level voltage to pins 9 and 14 of the K561LS2 microcircuit.

If it is required to increase the power of the pulses and the steepness of their rises and falls, TTL and TTLSH microcircuits should be used in the output stages of the ZG. On fig. 4 shows a diagram of a ZG on TTLSH microcircuits.

(click to enlarge)

The device allows pulse-width regulation of the output voltage of the UPS. The PWM node is assembled on the elements DD2.1, VT1, VT2, R3, C3, R5, R6. Voltage diagrams are shown in fig. 5. Here: Unop - threshold switching voltage of elements DD1.4 and DD2.1; tpf - fixed pause duration;

tp - adjustable pause duration;

tir - adjustable pulse duration; t and max, t and min - maximum and minimum pulse duration.

The pulse duration control interval is from 0,2 µs to 18 µs (at an output pulse frequency of 25 kHz). The duration of the pulses is regulated by changing the voltage at the base of the transistor VT1, which connects the resistor R5 in parallel with R6 and thereby changes the time constant of the differentiating circuit C3R6. Resistor R7 provides hysteresis and prevents self-excitation of the element DD2.1. The Uynp pin can receive a feedback signal from the UPS output voltage regulator.

When establishing the ZG, resistor R2 sets the duration of the pause, and resistor R5 sets the minimum duration (tn min) of the generated pulses (diagram k).

It should be noted that the use of PWM in a UPS is limited by the fact that with a decrease in the pulse duration less than t and max / 2, the efficiency of the UPS decreases sharply, since most of the time the switching transistors are in an unsaturated state. Therefore, the use of UPS with SHI output voltage stabilization is limited to a minimum load, usually not less than 10% of the nominal.

Of interest is the ZG (Fig. 6), which allows you to set the duration of the pause without time-setting differentiating circuits using counters K561IE8 (K561IE9).

The pause duration can be set discretely by changing the frequency of the clock generator and the counter division ratio within the limits indicated in the table for the frequency of the output signal of the ZG 25 kHz. The table shows that the pulse duration is equal to the period of the clock generator.

The ZG uses CMOS microcircuits having decimal counters with output decoders, however, this does not preclude the use of TTL and TTLSH microcircuits with output decoders. The division ratio is changed by connecting the feedback circuit (point e in the diagram in Fig. 6) to the input R of the counter and the output to the pulse distributor (point e) [2]. The frequency of the clock generator is regulated by changing the parameters of the R1C1 circuit.

Otherwise, the device does not differ from the above. Plots of voltage at the points of the circuit are shown in fig. 7 for the frequency of the output pulses of the MO 25 kHz, the duration of the pause 4 μs at a division factor of 5.

In principle, in all considered CGs (except for CGs with a discretely variable pause duration, Fig. 6), it is possible to apply the PWM control of the introduction of a feedback signal from the UPS output to the pause control unit, providing for the corresponding limitation of the minimum and maximum pulse duration.

For galvanic isolation of the UPS output voltage from the primary voltage source through the feedback circuit, it is most convenient and simple to use comparators in combination with optocouplers as the simplest and cheapest way.

However, the use of PWM leads to a complication of the filter in the DC circuit at the output, which sometimes negates the weight and size and economic indicators, especially at low UPS power and the requirement for a low output voltage ripple.

Literature

1. Kolganov A. Switching power supply of a powerful UMZCH. - Radio, 2000, No. 2, pp. 36-38.
2. Biryukov SA Application of TTL and CMOS series digital circuits. - DMK, 1999.

Author: V.Kozelsky

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