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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Digital frequency converter. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Digital technology Pulses with a stable repetition rate are usually formed from a crystal oscillator signal using a divider that lowers its frequency by the required (mostly integer) number of times. However, there are frequent cases when, due to the lack of the required quartz resonator, the ratio of the initial and required frequencies is not integer, and then it is necessary to use dividers with a fractional conversion factor [1, 2]. True, the period of the oscillations they form is not constant, but in some devices this does not matter. Readers are offered another version of such a device, the principle of operation of which is as follows. If we represent the generator signal frequency f as the sum of the required value fo and the absolute error dt, then to obtain the frequency fo it is sufficient to perform the subtraction operation: fo=f-df. In practice, it comes down to eliminating from the sequence of pulses with a repetition rate f of each pulse with the number n=f/df, rounded up to the nearest integer. For example, if f=10147 kHz, a fo=10000 kHz, then df=147 kHz and n=10147/147=69,27, i.e. 69. Therefore, excluding every 69th pulse from the original sequence, we get fo= ff/69==10147- 10147/69=9999,943 kHz. In this case, the relative error due to rounding off the number of the eliminated pulse is -5,7 * 10-6 and can be easily eliminated by adjusting the generator. The block diagram of the frequency converter that implements this method is shown in fig. 1. Counter D1, decoder D2 and reset and lock pulse generator G2 form a frequency divider with a conversion factor n. When a pulse with number n arrives from the quartz oscillator G1, a signal appears at the output of the decoder D2, which turns on the oscillator G2. The single pulse generated by it comes to one of the inputs of the D3 key, blocking it, and at the same time sets the counter D1 to zero. The delay line DT1 delays the pulses of the crystal oscillator G1 for a time equal to or slightly greater than the delay in the operation of the divider nodes. This ensures the simultaneous receipt of signals at the inputs of the switch D3, and if the pulse duration of the generator G2 is sufficient, the pulse with number n is excluded from the sequence. After that, a new cycle of operation of the converter begins.
A schematic diagram of a pulse converter of a quartz oscillator with a repetition rate f = 10143,57 kHz at n = 68 is shown in fig. 2. The crystal oscillator is made on the element DD1.1 according to the scheme described in [3]. Element DD1.2 - buffer. The counter is made on microcircuits DD2, DD3, the decoder - on the element DD4. The delay in the passage of pulses of the crystal oscillator to the key DD1.4 is provided by the R2C2 circuit. The delay time (t=R2С2) at the ratings indicated on the diagram is approximately equal to 16 ns. There is no explicit reset and blocking pulse generator. Its function is performed by the appropriately connected element DD1.3 and microcircuits DD2 - DD4.
The operation of the converter is explained by the timing diagram shown in Fig. 3. By the time the 2th generator pulse arrives at the inputs of the counter DD4 and decoder DD68 (Fig. 3, a), level 1 is set at all inputs of the decoder (Fig. 3, c-e) and with a delay for the turn-on time (tz.DD4) on its output is level 0 (Fig. 3, e), affecting one of the inputs of the key DD1.4. Due to the delay for time t, approximately equal to tg.DD4, the 68th pulse of the generator simultaneously arrives at the other input of the key (Fig. 3, b), however, it does not pass to the output of the device, since the key is closed (Fig. 3, h) .
After the delay time td.DD1.3 is switched and the element DD1.3 at the inputs RO of the counters DD2, DD3 level 1 appears (Fig. 3, g) and after the time td.reset the counters are set to zero. As a result, after the switching time ts.DD4, level 4 appears again at the output of the decoder DD1 (Fig. 3, f) and the key opens. The duration of the key blocking pulse is determined by the total delay time td.DD1.3+td.reset+td.DD4 and in the described case is approximately 60 ns. This is sufficient to exclude a pulse with a duration of about 50 ns from the sequence. The frequency values of the output signal obtained from the pulses of a quartz oscillator with a repetition rate f = 10 143,57 kHz for four options for connecting the decoder inputs to the counter outputs, corresponding to n = 67, 68, 70, 71, are summarized in the table, where dt is the repetition frequency of the blocking pulses at the output of the decoder (for measurements, a Ch3-33 frequency meter was used). As you can see, the frequency value closest to the required one (10000 kHz) is obtained at n = 71 (a further decrease in frequency is achieved by selecting capacitor C1).
With a duration of the quartz oscillator pulses that is longer than the blocking ones, the excluded pulses will partially pass to the output of the device and disrupt the process of obtaining a signal of the required frequency. The easiest way to eliminate this drawback is to increase the duty cycle of the pulses coming from the generator. The duty cycle converter can be performed according to the scheme shown in Fig. 4 and described in [4]. The timing diagram of its operation is shown in Fig.5. The device is connected between the elements DD1.1 and DD1.2 of the frequency converter. The pulses at the output of the element DD1.2 in this case will have a duration equal to the total delay time of the elements DD5.1-DD5.3 (45...55 ns) at any frequency of the crystal oscillator.
The described frequency converter has a wide range of additional features. Using the counter and decoder in full, it is possible to block every 2-256th pulse, i.e., change the division factor from 2 to 1'/256, and, by varying the capacitance of the counter and including several converters in series, to obtain accurate values and lower frequencies at lowest cost. The device can be used as a "splitter" of the input frequency into two components: fo and df. In this case, the pulses taken from the decoder output will have a constant repetition period, and the frequency division factor of the crystal oscillator signal will be equal to f / df. By setting logical keys between the outputs of the counter and the inputs of the decoder, you can directly control the division factor of the device with binary code signals and use it in code-to-frequency converters, in frequency modulators, etc. The converter can also be successfully applied for fractional frequency multiplication (not an integer number of times), by implementing the addition operation fo=f+df. To do this, it is necessary to "cut" each pulse with the number n=f/df into two parts, thus adding additional pulses to the original sequence. It is very simple to get the desired mode of operation: it is enough to transfer the R2C2 delay circuit to the circuit through which the pulses from the output of the DD4 decoder are fed to pin 12 of the DD1.4 element. In this case, the blocking pulse must be shorter than the generator pulse by at least 70 ... 100 ns (for K155 series microcircuits). With a short duration of the generator pulses, instead of the DD1.2 element, a duty cycle converter is included (Fig. 4). The timing diagram of the device operation in this case is shown in Fig. 6. In the multiplication mode, the converter was tested with a quartz resonator for a frequency f = 1014,36 kHz: with n = 68, the frequency fo = 1029,277 kHz was obtained.
It should be borne in mind that for reliable operation of the converter, it may be necessary to select the delay time t in the range of 10...30 ns. Literature 1. Biryukov S. A. Amateur radio digital devices.- M .: Radio and communication, 1982, p. 16.
Author: A. Samoilenko, Novorossiysk; Publication: N. Bolshakov, rf.atnn.ru
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