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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Control of field-effect transistors in pulse converters. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Radio amateur designer As you know, the use of powerful field-effect transistors instead of bipolar ones in pulse voltage converters provides a number of advantages. You can read about this in the special literature, however, firstly, it is practically inaccessible to the average reader and, secondly, the issues of controlling powerful field-effect transistors are set out in it, as a rule, in a general form, without reference to specific circuits, a detailed description of the work converters are missing. The author of this article introduces the features of the use of field-effect transistors in such devices. The field-effect transistors of the MIS structure with an induced n-channel are the most widely used in pulse voltage converters. At zero voltage at the gate (with respect to the source), the transistor is closed and opens with a positive voltage with a fairly clearly defined threshold. On fig. Figure 1 shows the experimentally measured dependence of the drain current on the gate-source voltage of the IRF630 transistor. The input voltage interval from a fully closed state to a saturated state does not exceed 0,5 V, which means that the transistor is typically switching.
Since there is no accumulation of charge carriers in the channel, there is no time for their resorption. The duration of the rise and fall of the drain current pulses with a corresponding control signal is 20 ... 30 ns at a full operating current reaching 9 A. The maximum operating drain-source voltage Us max = 200 V, the maximum dissipated POWER P pac max = 75 W. The input resistance of MIS transistors is purely capacitive, but this does not mean that when a control pulse is applied to the gate, it will behave like a conventional capacitor. On the equivalent circuit of a transistor, three main capacitances are distinguished: input Czi - between the gate and the source; the passage Cse - between the drain and the gate, the output Cci - between the drain and the source. The capacitance Sei is charged like a conventional capacitor only up to the threshold voltage Upor. As soon as the transistor opens, a negative voltage feedback occurs through the capacitance Ссз. A horizontal section appears on the charging curve of the input capacitance. Its duration, depending on the charging current, is from fractions to units of microseconds, however, it plays an important role in the formation of the drain current pulse. To study the features of the charging curve, a node was assembled, the diagram of which is shown in Fig. 2 (without resistor R3). The node is powered by two sources Upit1 and Upit2, since the drain voltage reaches hundreds of volts.
Stress diagrams at the characteristic points of the node are shown on an arbitrary scale in Fig. 3.
Until the moment, the positive voltage at the input keeps the transistor VT1 open. The duration of the rise and fall of the triggering pulses (total with the rise time of the oscilloscope amplifier) did not exceed 20 nsec, so they are not shown in the diagram. On the segment t1 ... t2, when the transistor VT1 is already closed, VT2 is also still closed and the voltage at its gate increases exponentially with the time constant R2Czi. On the screen, this initial section looks like a straight line segment. Transistor VT2 opens at time t2, i.e. with some delay. Let's designate it as tset1 = t2 - t1. From the moment t2, a negative feedback begins to act between the drain and the gate through the capacitance Ссз (Miller effect). The voltage at the gate stops increasing, and graph b in the section t2 ... t3 is a horizontal line on the screen. On the other hand, the voltage at point b from the moment t2 begins to decrease due to an increase in the drain current. At the moment t3, the transistor VT2 opens completely, the voltage at its drain almost reaches zero and remains constant, the negative OS is turned off through Cse (the OS current is zero). The gate voltage again begins to increase exponentially up to Upit1. At the moment t4, the transistor VT1 opens and the capacitance Czi starts to discharge. The time constant of its discharge is much less than charging, so the voltage at the gate of the transistor VT2 decreases very quickly, and until it reaches the Unop value (moment t5), the transistor VT2 remains open. At time t5, it starts to close, the voltage on its drain starts to increase, and the negative FB kicks in again. A step appears on chart b, but since the close is very fast, its duration is very short. The transistor turns off before the voltage at its gate drops to zero. The time interval from U to t5 is the switch-off delay time tset2 = t5 -t4. One of the most important conditions for the reliable operation of pulse voltage converters is the formation of a safe switching mode for powerful transistors. When the transistor is turned on, the drain current increases from zero to a maximum, and the voltage across it decreases from a maximum to almost zero. When the transistor closes, the process is reversed. It is necessary that both current and voltage, and their product throughout the entire trajectory of the operating point, do not exceed the allowable values. Current and voltage surges in transitional positions must be excluded or minimized. These goals are achieved by forced slowing down of the switching processes of transistors. At the same time, the rise and fall of the pulse should be as short as possible in order to reduce heat generation in the transistor, i.e., a compromise must be found. Experiments show that with field-effect transistors the problem is solved more easily than with bipolar ones. The rise time of the drain current pulse is equal to the duration of the horizontal section t2...t3, which, in turn, is proportional to the resistance of the resistor R2 (see Fig. 2). The dependence of the front duration tf, on the resistance of the resistor R2 is shown in fig. 4. Therefore, by selecting this resistor, you can easily set the desired rate of rise of the drain current.
Turning on the field-effect transistor according to the scheme of fig. 2 has one interesting feature that contributes to the solution of the problem. The rate of rise of the drain current in the initial phase of the pulse is noticeably reduced, resulting in the complete absence of a surge at the front of the drain current pulse (the shape of the drain current pulse can be judged by the shape of the voltage pulse at point c) The opening time of a powerful field-effect transistor is approximately the same as that of a bipolar , included according to the corresponding scheme, and the closing time is ten times less. So, for the IRF630 transistor with Upit1 \u15d 2 V and R560 \u0,5d 0,06 Ohm, topen = 7,5 μs, tclose = 20 μs. With such a HIGH closing SPEED, the drop of the drain voltage pulse has a surge of 20 V at Up = 27,5 V. The pulse amplitude is also XNUMX V, which means that the surge is XNUMX% of its amplitude. Some consider the surge to be due to the direct passage of the input signal through the capacitance Cse. I believe that the power of the input signal is too low for this, although, of course, there are conditions for passing. A more likely cause, I believe, is the reaction of the transistor power circuit to a rapid decrease in drain current. In any case, this phenomenon must be fought. The easiest way is to reduce the surge by increasing the discharge time of the input capacitance of the transistor VT2 (see Fig. 2). To do this, a resistor R1 was included in the emitter circuit of the transistor VT3. At R3 = 56 Ohm, the amplitude of the surge decreased to 1,75 V or 9%, and at R3 = 75 Ohm, to 1 V or 5% of the pulse amplitude. With resistor R3, the duration of the pulse front increases slightly - by about 0,1 μs. Completely undistorted pulses are obtained if a circuit of a series-connected capacitor with a capacity of 0,47 ... 1 μF and a resistor with a resistance of 1 ... 2 Ohm is connected to the upper terminal of the load resistance Rн (the second end of the circuit is connected to a common wire). This circuit should be placed as close as possible to the terminals of the transistor VT2. In push-pull converters, in addition to those listed, another problem appears - through current. The reason for its appearance in devices based on bipolar transistors is the finite time of absorption of excess minor carriers in the base of transistors, which is why it is necessary to artificially delay the opening of transistors. In field-effect transistors, under these conditions, the turn-on and turn-off delay occurs automatically and the duration of the delays is stable. Despite the fact that there is no charge accumulation in field-effect transistors, a through current can appear only when tset2 > tset1. If you ensure that the transistor closes in one arm of the converter before the closed one opens in the other arm, this current will not occur. In other words, there must be a pause between the closing of one transistor and the opening of another. To open a field-effect transistor, relatively little power is required. Control pulses can be applied directly from the outputs of logic circuits without prior current amplification. The output power of the converter itself can reach several hundred watts. To control powerful field-effect transistors, the industry produces special microcircuits that allow an output current of up to 100 mA or more. But these are universal microcircuits, designed to control transistors with Svx \u3000d 4000 ... XNUMX pF and a conversion frequency of hundreds of kilohertz. A fragment of the switching circuit for transistors controlled by digital microcircuits is shown in fig. 5 The input capacitance of transistors VT1 and VT2 is charged through resistors R1 and R2, and discharged through diodes VD1, VD2, respectively, which is equivalent to switching on according to the circuit in fig. 2.
On fig. 6 shows on different time scales the drain current pulses of transistors VT1 and VT2. The signal on the oscilloscope screen looks like a straight line with narrow teeth (Fig. 6, a). The spikes are short pauses between drain current pulses. The shape of the pause on a large time scale is shown in Fig. 6b. The signal can be observed on the screen of a two-channel oscilloscope in the "sum" mode with inversion in one of the channels.
However, the diagram in Fig. 5 is not typical for building powerful switching power supplies. They most often use half-bridge voltage converters, in which the control circuits of powerful transistors must be isolated from one another in direct current. A diagram of a half-bridge converter (in a simplified form - without some auxiliary nodes) is shown in fig. 7. The device according to the scheme of fig. 5 is used here as a control pulse generator and an additional power source.
This converter operates at 25 kHz; output power - 200 W. The master oscillator on the logic elements DD1.1, DD1.2 of the CD4011BCN chip works very stably. With another microcircuit, the frequency may differ from the indicated one, then the resistors R2 (and, possibly, R3) will have to be selected. It is undesirable to use the K561LA7 microcircuit, since the supply voltage of the master oscillator is 15 V, i.e., the maximum allowable for this microcircuit. IRFD010 transistors have a small input capacitance, which is why the pauses between pulses do not exceed 0,5 µs. The duration of pauses can be increased by connecting capacitors C5 and C6 (shown by dashed lines) with a capacity of 100 pF or more. They can symmetrical pauses. If the pauses are symmetrical, then they can be expanded more easily by including a capacitor between the gates of transistors VT1 and VT2. In this case, the duration of the rise and fall of the pulses increases insignificantly. The symmetry of the pulses themselves is achieved by selecting the resistor R2. For the described transducer, the duration of the pause at the base of the pulses is 0,1 µs and approximately 0,45 µs between their peaks. The pulses coming from the windings III and IV of the transformer T1 open powerful transistors VT3 and VT4. Such an inclusion of transistors is equivalent to that shown in the diagram in Fig. 2 with resistor R3 The shape of the pulses on the primary winding of the transformer T2 on an arbitrary scale is illustrated in fig. 8.
Resistor R6 plays an important role in the device. It eliminates surge at the pulse front and suppresses resonant phenomena. It is convenient to take a signal from it to observe and control the parameters of pulses and pauses between them. His resistance should be the minimum necessary to achieve these goals. Author: M.Dorofeev, Moscow
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Comments on the article: Alexander Very intelligible. Even for me, I'm just getting started. Thank you.
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