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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Computer-based logic analyzer. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Computers Public literature on computer topics is mainly devoted to the traditional use of a personal computer (PC) - for calculations, creating and editing documents, searching and storing information, and entertainment. Less common are articles and books about designing various electronic devices using a PC. There are almost no materials about how a PC can help a radio amateur in setting up and debugging the devices he creates. It is believed that for this the PC must be equipped with rather complex and expensive additional boards and set-top boxes. However, often a number of functions that are very useful to a radio amateur can be implemented using standard devices available in each PC, such as communication ports. This will be discussed in the proposed article. Each IBM-compatible PC has two serial communication ports, referred to as COM ports or RS-232C interfaces. A mouse manipulator is usually connected to one of them, without which it is difficult to imagine effective work today, the second one often remains free or is used from time to time to connect an external modem and other peripheral devices that do not work all the time. The set of RS-232C interface signals and their purpose are described in detail in [1]. All of them are listed in Table. 1 together with RI (Ring Indicator, circuit 125) not mentioned in the same article. As you can see, the user has three output and five input circuits. A program that generates signals of the required shape at the outputs of a COM port and simultaneously analyzes the state of its inputs can turn a PC into a memory multichannel logic analyzer with a wide range of analysis periods and rich synchronization, processing and displaying capabilities. It can be useful when debugging a wide variety of digital devices.
The main difficulty in developing an analyzer program is that the standard hardware and software configuration of an IBM-compatible PC, even in the presence of a fast processor and RAM, does not allow any accurate formation of intervals less than a few hundred milliseconds using DOS processor interrupts due to system timer overflow. , and on Windows, timer messages. Since these events occur with a period of approximately 55 ms, this is how the “quantum” of the time count turns out. Attempts to reprogram the timer lead to unpredictable consequences for all running programs and the operating system itself. You can measure time by counting the number of cycles a program has run, and by making sure that this process is not interrupted by external events. But even such a task in modern operating systems is not solved correctly, in addition, shutter speed adjustment is required in relation to each PC hardware configuration. In MS DOS, such problems are solved more easily, but the development of a program becomes too laborious if a graphical interface and auxiliary actions are required: calculations, printing graphs. However, using any operating system, you can get a signal of a strictly specified frequency and shape at the TXD output of the serial port. As you know, the bit rate of the transmitted data is equal to the division of the reference frequency stabilized by the quartz resonator (115 200 Hz) by the coefficient M. The system software selects and sets this coefficient based on the standard information transfer rates. However, nothing prevents an application program from assigning the M factor any value between 1 and 216 -1 (0FFFFH). Thus, pulses with a frequency from 57,6 kHz to fractions of a hertz can be obtained at the TXD output, and an arbitrary frequency below 12 kHz can be set with an error of no more than +10, and below 1,2 kHz - +1%. The serial port is controlled through ten eight-bit registers of its controller, called a universal asynchronous transceiver (UART, UART). In table. 2 shows the addresses of these registers in the PC input-output space and their functional purpose. It is easy to see that some of them have the same addresses. Access to others is additionally controlled by the most significant bit (D7) of the line control register. If it has a logical 1, they access the speed divider registers (high and low bytes of the number M), if 0 - data of the transmitter and receiver, enable interrupts.
The TXD output signal format depends on the code written to the line control register. Bits D1 and D0 of this code set the number of information bits in a word transmitted (or received) by the UART. There can be from five (in the mentioned digits - code 00) to eight (code 11). The number of stop bits depends on the state of the D2 bit: 0 - one; 1 - two. With five information instead of two stop bits, one is transmitted, but one and a half duration, which is done for compatibility with old mechanical teletypes. Bits D3-D5 of the line control register control the parity bit. If D3=1, during transmission it is "inserted" between the last information and the first stop bits, otherwise it is absent. The transmitter automatically selects the value of this bit so that the total number of ones in the information and control bits becomes even (with D4=1) or odd (with D4=0). This logic can be disabled by setting D5=1. The control bit will become the inverse of the value of the D4 bit, regardless of the number of ones in the information bits. Logic 1 in bit D6 enable the simulated disconnection mode. At the TXD output, regardless of the state of all other bits and registers, a constant logic level of 0 is set. The purpose of bit D7 was described above. In table. 3 shows some examples of the formation of signals of various frequencies and duty cycles in the TXD circuit, far from exhausting all the possibilities. The waveform shown in the corresponding column of the table can be observed directly at the TXD output of the UART. On the external connector of the port, it is inverted. However, the interface device described below will invert the signal again and its shape will again coincide with the table.
Recall that the transmission of a byte written to the transmitter data register starts with the least significant bit. Since a byte is transferred only once, in order to obtain a strictly periodic output signal, it is necessary to repeat the loading of the specified register immediately after it is freed. The readiness to write a new byte is indicated by D5=1 in the line status register. If you do not want to spend time constantly polling the status register, you can use interrupts. Typically, the port controller COM1 generates an IRQ4 request, and COM2 generates an IRQ3 request. The generation of interrupt requests when the transmitter is ready must be enabled by writing a logical 1 to bit D1 of the interrupt enable register. When requests are simultaneously allowed for other reasons, when processing them, you should first of all read the interrupt identification register and, only after making sure that there is a binary code 2 in its bits D1 and D10, write a new byte to the transmitter data register. The signal levels at the RTS and DTR outputs depend on the state of the D1 and D0 bits of the modem control register. It is recommended that bits D2 and D3 of this register be written to logic 0. But in some PCs, a zero value of bit D3 disables the UART from the interrupt controller. If you enter a logical 1 in bit D4, the TXD and RXD circuits will be interconnected inside the UART (the so-called "internal loop"), which can be used for debugging and diagnostic purposes. Bits D4, D5, D6 and D7 of the modem status register display the current signal levels at four inputs - respectively CTS, DTS, RI and DCD. A very useful property of the UART is to fix the facts of the change in the state of the named circuits in units in the bits D0-D3 in the intervals between program calls to this register. Interrupts are also provided for changing the state of the modem. They correspond to bit D3 of the interrupt enable register and code 11 in bits D2 and D1 of their identification register. Unfortunately, the main RXD input circuit when using the serial port for its intended purpose is not of great interest for the task under consideration. More details about the purpose and use of UART registers can be found, for example, in [2]. The logic levels of the signals at the inputs and outputs of the serial port must be within -3...-15 V (logical 1) and +3...+15 V (logical 0). To debug devices based on TTL and CMOS chips, these levels must be converted accordingly. This can be done using the interface node, the diagram of which is shown in Fig. 1. The elements of the DD1 chip convert the output signals of the port to the required levels, and the switches on transistors VT1-VT4 will perform the reverse conversion. Switch SA1 can connect one of the port inputs directly to the TXD output. This may be necessary to clock the analysis process.
The XS1 plug is connected to the PC serial port socket with a cable up to several meters long, the device being debugged is connected to the XS2-XS11 sockets. It is best to power the interface node and the device being debugged from a common source. Often in the device being debugged there is no negative voltage necessary to power the collector circuits of transistors VT1-VT4. In this case, they are fed by the "rectified" diodes VD1-VD3 with the negative voltage of the output signals of the port, which are in the state of logical 1. The signal generator and logic analyzer program developed by the author works in a 32-bit Windows environment. Its main window "Analyzer", shown in Fig. 2 is a screen of a virtual four-channel (by the number of port input circuits) storage oscilloscope. To the left of the screen are indicators ("light-emitting diodes") that make it easier to observe slow processes. After starting the program, you must select the communication port with which it will work in the "Port" menu.
The oscilloscope sweep can be continuous with a specified period or single (start by pressing the corresponding button). The "Stop" button can be used to "freeze" the image. Having opened the "Synchronization" window (Fig. 3), select any of the input or output signals as the synchronizing one.
In the "Sweep" window (Fig. 4) set the clock frequency of the analysis and its duration.
The "Output line modes" dialog box, in which the frequency and shape of the generated signals are set, is shown in fig. 5. The clock division ratio is changed with a decade switch. The program calculates and displays in the window the frequency and repetition period values corresponding to the given coefficient and the selected signal shape at the TXD output. Generation can be continuous, single or bursts of a given number of pulses.
The DTR and RTS signal levels are set using the "0" and "1" buttons. In addition, these outputs can receive a "square" or arbitrary waveform. The author's program of the signal generator and logic analyzer Literature
Author: A. Schreiber, Moscow
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