ISD4004-16M is a single-chip voice recording/reproduction system. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Microcontrollers

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Using a technology patented by Information Storage Devices (ISD; part of Winbond Electronics Co. since 1998), an analog signal received at the corresponding input of the ChipCorder chip can be stored in its natural form directly in a standard non-volatile EPROM (EEPROM) and cells in flash memory. The technology of the so-called "false differentiation" lies in the fact that instead of storing one of the two values ​​​​in the cell - 0 or 1 - one of the 256 voltage levels is stored. This provides a significant capacity advantage over the conventional way of storing a digitized signal. In addition, this technology for recording and storing speech does not require analog-to-digital conversion, which greatly simplifies the circuit of a complete device based on a microcircuit.

ChipCorders for speech recording/playback can be operated from low-power power supplies. This makes them ideal for building lightweight portable products, including those with battery power.

Additionally, as common features of the family, we can name the AutoMute mode, which provides noise reduction during pauses, the automatic transition to the standby state at the end of the recording / playback cycle (current consumption in standby mode is 0,5 mA), the use of non-volatile memory, adjustable duration recording, full addressability via SPI or Microwire interface.

The ISD4004-16M chip samples at a sampling rate of 4 kHz. Speech samples are stored directly in the non-volatile Flash memory on the chip without digitization and compression, typical for other types of speech recording. The message can be stored for up to 100 years (typical; tested using the accelerated calculation equivalent method) without power. In addition, the device can be overwritten over 100 times. Analog direct memory ensures natural-sounding playback of voices, music and sound effects. The maximum recording time is 000 minutes.

The block diagram of the ISD4004-16M is shown in fig. 1. As you can see, the chip includes a clock generator, a microphone amplifier, an anti-aliasing filter, a multi-level memory array, an anti-aliasing filter, a silence noise reduction device, and a 3-hour output amplifier.

Four-wire (SCLK, MOSI, MISO, SS) serial peripheral interface (Serial Peripheral Interface - SPI) provides control and addressing. In a system with a microcontroller, the chip acts as a peripheral slave. Write/read access to all internal registers is via the SPI interface. The interrupt signal (INT) and the internal status register are used only for reading and establishing communications.

To minimize noise, the analog and digital circuits in the device are connected to separate power buses, Ucca and Uccd, respectively. The nominal supply voltage is 2,85 ... 3,15 V. Ussd) parts in ISD4004-16M are also made separately. The bottom of the crystal is connected to Uss through the substrate resistance. In miniature versions (unframed), the crystal is attached to the area associated with Uss. or may remain "floating".

An analog input signal can be fed into the device either in asymmetric mode (Fig. 2, a) or differential (Fig. 2, b). In the first case, the signal is connected to the analog input+ (ANA IN+), and the input- (ANA IN-) is connected through an isolation capacitor to the common wire bus Ussa- For high-quality reproduction, the double amplitude of the input signal in this mode should not exceed 32 mV, which corresponds to double amplitude 570 mV at the output. The decoupling capacitor at the ANA IN+ input, together with the 3 kΩ input impedance of this input, determines the low frequency bandwidth.

In differential mode, both inputs (ANA IN+ and ANA IN-) are used. For optimal quality, the peak-to-peak signal at each of the inputs in this case should not exceed 16 mV. The impedance of the ANA IN- input is 56 kΩ.

From pin 13 (Fig. 1), the sound signal recorded in the ISD4004-16M memory is removed. It is recommended to connect this output to the load through a decoupling capacitor. The load impedance must be at least 5 kOhm. During operation (with power on), the AUD OUT pin is 1,2V DC. When recording, the AUD OUT is connected through a resistor of approximately 850kΩ to an internal 1,2V supply to analog ground. The load in this mode can be connected, but the constant voltage at the output of the device must not decrease.

The SS (Slave Select) pin selects the slave device. When a low signal is applied to this pin, the ISD4004-16M is selected as the master to work with the microcontroller.

MOSI is a serial input through which data is transferred from the microcontroller. The data in the MOSI line is set half a cycle before the arrival of the clock edge, also received by the BISD4004-16M.

The MISO pin is the serial output from the device. If no device is selected (SS = 1), the output is in the high impedance state.

The SCLK pin is used to receive the clock from the microcontroller to synchronize data transfer to and from the device via the MOSI and MISO buses. Data is written to the ISD4004-16M during the rising edge of the clock pulse, and when it falls, the information is shifted to the next bit.

The INT (Interrupt) pin goes low and stays low (log 0) if an overflow (OVF) occurs or the marker detects an "End of Message" (EOM). This pin is an open drain output. Every operation that ends with an overflow or has an "End of Message" generates an interrupt, including the instruction to call the message loops. The next time the interrupt will be cleared is when a new SPI cycle is initiated. The interrupt status can be read with the RINT instruction.

The overflow flag OVF indicates that the analog memory during a recording or playback operation has reached the end, and the "End of Message" (EOM) is set only in playback mode when an EOM signal is detected. There are eight options for the position of the "End of Message" flag on a single line (ie, eight different messages can be written in it).

The RAC output (address line synchronization) is also open drain. When recording, a signal is applied to it with a period of 400 ms when a signal is sampled at a frequency of 4 kHz. For the specified period, only one line of memory is written (there are 2400 such lines in total). Accordingly, recording is performed for 350 ms when the RAC signal is high. When the end of the line is reached, the RAC signal goes low for 50 ms. The cyclogram for recording one line is shown in fig. 3.

In the Message Call mode (see below), the RAC pin is held high for 218,76 µs and low for 31,26 µs. For typical RAC clock levels, refer to the AC parameter table in the company documentation.

When a write command is first initiated, the RAC pin remains high for an additional period of TRACL0. This is required to download the sample and fix the internal systems of the device. The RAC pin can be used to control the message technique.

The external clock input has an internal matching device. The ISD4004-16M instruments are factory configured to internally sample the input signal at the center clock frequency with a tolerance of ±1% of specification. Within tolerance frequency is maintained at any value within the extended industrial temperature range as well as within the operating voltage range as defined in the appropriate AC rating table. When operating in the industrial temperature range, a regulated power supply is recommended.

If high accuracy is required, then for sampling at a frequency of 4 kHz, a clock with a repetition rate of 512 kHz must be applied to the device through the XCLK pin. For the built-in anti-aliasing filters to work properly at a fixed frequency, the clock frequency must be sufficiently stable. The duty cycle of the clock pulses is not critical, since their frequency is immediately divided by 2. If the XCLK input is not used, pin 26 must be connected to the common wire.

The AM ATS pin is used to control the automatic noise reduction. The latter reduces the signal level by 6 dB if it falls below the set threshold (noise reduction is not enabled for large signals).

For normal operation of the noise reduction system, the AM ATS output is connected to a common wire through a 1 μF capacitor. This capacitor becomes an element of the internal peak sensor, which responds to the amplitude (peak value) of the signal. The peak level is compared to the set threshold to determine when the noise reduction is activated. The capacitor also affects the rate at which the noise reduction changes over attack time as a function of signal amplitude. Connecting the AM CAP output to the Ucca bus disables noise reduction.

As noted, the ISD4004-16M uses a serial SPI interface. The data transfer protocol assumes that the shift registers of the microcontroller are synchronized on the fall of the SCLK signal. In the ISD4004-16M, data is latched onto the MOSI pin on the rising edge of the clock. Data is received from the MISO output by the fall of the clock pulse.

1. All serial data transfers start with a falling signal on the SS pin.

2. This pin is held low for the duration of the serial communication and goes high between commands.

3. Input data is captured on the rising edge of the clock pulse, and output data is captured on the falloff.

4. Playback and recording are performed at low level on the SS pin when the corresponding operation code and address are supplied to the ISD4004-16M device.

5. Operation codes and address fields are represented by eight service and 16 address bits.

6. Each operation ending with an End of Message (EOM) or Overflow signal generates an interrupt, including the Call Message Loop instruction. The interrupt is cleared the next time a new SPI cycle is entered.

7. Since the interrupt data is shifted without saving the advance bits in the MISO, the control data and addresses on the MOSI pin are shifted at the same time. Caution is advised as shifted data may be compatible with the current system operation. It is possible to read interrupt data and start a new operation within the same SPI cycle.

8. The operation starts with the Run bit (RUN) set and ends with its reset.

9. All operations start on the rising edge of the SS pin.

The Call Message command, which allows the user to "jump" through messages if the actual location of the person of interest is not known, is used during playback. In this mode, the pass speed is 1600 times faster than normal playback. The stop occurs when the marker indicates "End of message". The internal address counter will then point to the next message. If the Call Message (MC) command is used, the following procedure must be followed, otherwise the call may not be accurate.

The procedure for correctly calling a message is as follows. Before executing or setting the "Message Call" command (MC or SETMC, respectively), one "idle" (dummy) Stop command must be sent to the device. Such a command consists of a set of service bits: "Pass" = 0, "Play / Record" = 0, PU ("Power on") = 1, IAB ("Skip address") = 1, MC ("Recall message") = 0. In other words, the hexadecimal number 30 is used as a command in the device. After the "dummy" Stop command is entered, one or more MC commands or a SETMC command may be executed. There is no need to repeat the "idle" Stop command before the end of the next playback operation. Operational codes are presented in table. 1.

Power-up sequence. The ISD4004-16M is ready for operation after TPUD time (typical value at 4 kHz sample rate is approximately 50 ms). You must wait this time before issuing an operation command. For example, to play from address 00, the following program loop would be used:

1. A POWERUP command is sent to turn on the power.

2. Pause for TPUD (Power On Delay).

3. The SETPLAY command with address 00 is issued.

4. The PLAY command is sent

As a result, the device starts playback from address 00, and when the "End of Message" occurs, it generates an interrupt. After that, playback stops.

Loop to implement write mode:

1. A POWERUP command is sent.

2. Pause for TPUD (Power On Delay).

3. The POWERUP command is issued.

4. The SETREC command is sent with address 00.

5. The REC command is sent.

The device starts writing a message from address 00, and when an overflow occurs (end of the memory array), it generates an interrupt, after which the recording stops.

A simplified block diagram of the SPI port with a description and indication of the control bits associated with it is shown in fig. 4, a and b.

The SPI control register provides control of device functions such as playback, recording, message recall, power on and off, start and stop operations, address skip. In table. 2 shows the values ​​in the bits of the SPI control register and their corresponding functions.

Timing diagrams of the operation of the ISD4004-16M chip when control commands (8 bits) and addresses (16 bits) are given in a 24-bit format are shown in Fig. 5.

(click to enlarge)

Diagrams in fig. 6 illustrate a recording/playback and stop cycle.

(click to enlarge)

All timings can be found in the already mentioned AC parameter table.

On fig. 7 shows a diagram of a possible option for connecting the ISD4004-16M chip to the common PIC16C62A microcontroller and the LM3M 4860H integrated power amplifier.

(click to enlarge)

When developing devices using the ISD4004-16M, it should be remembered that for reliable and trouble-free operation it should be powered by a stabilized voltage that does not go beyond 2,85 ... in close proximity to a power source.

The USSA analog ground pin should be connected to the power supply common by a line with the lowest possible impedance, and the USSD digital ground pin should be connected to a separate low-impedance bus. The busbars connecting the analog and digital inputs to the common wire of the power supply must be large enough to guarantee a minimum voltage drop across them. In this case, the difference in the impedance of the tires should not exceed 3 ohms.

Author: A.Shitikov

See other articles Section Microcontrollers.

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