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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Infrared light control system. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / infrared technology Description The infrared control system described here has increased noise immunity, which is achieved by multiple transmission of commands. In this case, the decoder issues a signal about the reception of the corresponding command only if at least two of the three commands received in a row contain the same information. Transmitter Pulse code is used to transmit commands. The transmitter encoder is built on two digital CMOS microcircuits of the 561 series (Fig. 1, DD1, DD2). On the elements DD1.1 and DD1.2, a rectangular pulse generator is assembled, operating at a frequency of about 200 Hz. Due to the fact that the switching threshold of CMOS elements does not correspond exactly to half the supply voltage, elements R2 and VD1 are added to the traditional oscillator circuit to balance the pulses. The generator pulses are fed to a counter with decoders (DD2 microcircuit), which normally has a conversion factor of 10. At those moments when the counter is in state 0 or 1, there is a logical 0 at pins 1 or 3 (pins 2 or 1, respectively), which prohibits the passage generator pulses through the element DD1.3 to the buffer element of the transmitter. In other states of the counter, positive polarity pulses pass to the buffer element of the transmitter. As a result, if none of the SB1-SB7 buttons is pressed, bursts of eight pulses arrive at the transmitter's buffer element, separated by an interval equal to 2.5 pulse periods. The transmission of such packets corresponds to the absence of commands.
Let's consider how commands are formed using the example of a command containing 5 pulses. If you press the button SB5, the counter, as before, prohibits the passage of the first two pulses to the modulator. Then 5 pulses pass to the transmitter buffer, after which the counter is set to state 7 and a logical 7 is set at its output 6 (pin 2 DD1). This signal is fed through the closed contacts of the SB5 button to the input R of the counter DD2 and resets it to 0. As a result at pin 10 of element DD1.3, bursts of five pulses are formed, separated by intervals of the same duration as in the absence of command transmission. When you press any other button, bursts are generated corresponding to the button number with the number of pulses - from one to eight, separated by the same interval. The IR transmitter is a buffer element (DD3.1, DD3.2), a carrier frequency generator (25-30 kHz.) (DD3.3, DD3.4) and an amplifier (VT1). The carrier frequency generator is modeled in terms of amplitude by bursts of pulses coming from the encoder. An IR emitting LED is included in the collector circuit of the transistor VT1, and it sends an exact copy of the encoder signal into space. Receiver The receiver is assembled according to the classical scheme adopted in the Russian industry (in particular, in Rubin, Temp TVs, etc.). IR radiation pulses fall on the IR photodiode VD1, are converted into electrical signals and amplified by transistors VT3, VT4, which are connected according to a common emitter circuit. An emitter follower is assembled on the transistor VT2, matching the resistance of the dynamic load of the photodiode VD1 and the transistor VT1 with the input impedance of the amplifier stage on the transistor VT3. Diodes VD2, VD3 protect the pulse amplifier on the transistor VT4 from overloads. All receiver input amplifier stages are covered by deep current feedback. This provides a constant position of the operating point of the transistors, regardless of the external illumination level - a kind of automatic gain control. This is especially important when the receiver is used indoors with artificial refreshment or outdoors in bright daylight, when the level of extraneous IR radiation is very high. Next, the signal passes through an active filter with a double T-shaped bridge, assembled on a VT5 transistor, resistors R12-R14 and capacitors C7-C9. It cleans the coded signal from AC interference emitted by electric lamps. The lamps create a modulated radiation flux with a frequency of 100 Hz. and not only in the visible part of the spectrum, but also in the IR region. The filtered signal of the code message is formed on the transistor VT6. The carrier frequency is no longer needed and is suppressed using the simplest RS filter on R18, C14. The result is a signal that is completely identical to that taken from the output of the command encoder. Packets of input pulses of negative polarity are fed to the shaper, assembled on the elements R1, C1, DD1.1. Such a shaper has the properties of an integrating chain and a Schmitt trigger. At its output, the pulses have steep fronts, regardless of the steepness of the fronts at the input. In addition, it suppresses impulse noise of short duration. From the output of the element DD1.1, the pulses are fed to the pause detector. It is assembled on the elements R20, C13, VD4, DD1.2. Just like DD1.1, DD1.3, the XOR element "DD1.2 works as an amplifier - signal repeater, since one of its inputs is connected to a common wire. The pause detector works by the following loop. The first negative pulse of the burst, passing through diode VD4 to the input of element DD1.2, switches it to state 0. In the pause between adjacent pulses, the capacitor C13 is gradually charged by the current flowing through resistor R20, the voltage at the input DD1.2, however, does not reach the switching threshold of this element Each subsequent pulse through the VD4 diode quickly discharges the capacitor C2, therefore, during the burst, the output of DD1.2 will be logical 0. In the pause between the bursts, the voltage at the input 5 of DD1.2 reaches the switching threshold, this element switches in an avalanche-like manner due to positive feedback through the capacitor C13 to state 1. As a result, in the pause between bursts, a positive pulse is formed at the output 10 of the DD1.2 element (fourth diagram in Fig. 4), resetting the counter on the DD2 chip to 0. The pulses from the output of the DD1.1 shaper also go to the counting the output CN of the counter DD2, as a result of which, after the end of the burst, the counter is set to the states corresponding to the number of pulses in the burst (and hence the command number). As an example, in fig. 4 shows the operation of the counter when receiving a burst of five pulses. The front of the pulse from the pause detector rewrites the data from the counter into the shift registers DD3.1, DD3.2, DD4,1, as a result of which a logical 1, 1, 0 appears on their outputs 1, respectively. After the end of the second burst of five pulses, the pulse with the output of the pause detector shifts the previously recorded information from bits 1 of the shift registers to bits 2, in bits 1 it writes the result of counting the number of pulses of the next burst, etc. As a result, with continuous reception of bursts of five pulses, all outputs of the shift registers DD3.1, DD3.2, DD4.1 will be logical 1, 0, 1, respectively. These signals are fed to the inputs of the major valves of the DD5 microcircuit, signals corresponding to the input appear on their outputs, they are fed to the inputs of the DD6 decoder. At the output 5 of the decoder, a logical 1 appears, which is a sign of the receipt of this command with the number of pulses equal to five. This happens when receiving commands without interference. If the level of interference is strong, the number of pulses in the burst may differ from the required one. In this case, the signals at the output of the shift registers will differ from the correct ones. And the major valves will ignore the wrong signal. Thus, if in the sequence of bursts of pulses entering the input of the command decoder, in any three consecutive bursts, two have the correct number of pulses, a logical 6 will be constantly maintained at the desired output of the DD1 chip. If none of the transmitter buttons is pressed or the transmitter is not turned on at all or there is no reception signal, the outputs 1-2-4 of the DD2 counter will have a logical 0 after the end of a burst of eight pulses, and all used outputs of the DD6 decoder will also have a logical 0. Further signals from decoder, commands are sent to the brightness control assembled on the elements DD7-DD13, R21-R30, VD5, VS1, C14-16, VT7. In particular, commands 1, 3, 5, 7 are used respectively "on", "off", "more", "less". For simultaneous control from the remote control and from the regulator itself. Signals from the decoder and from the control buttons, 2OR-NOT (DD12) and 4OR-NOT (DD8) logic elements are installed. The first ones are set for smooth adjustment, the second ones are also suitable for turning on and off, the counter set limiters DD10) and the reset unit. The smooth adjustment unit includes buffer inverters DD12.1 DD12.2, adjustment speed generator (DD9.1, DD9.2) and switches (DD9.3, DD9.4). The dimmer works as follows, the command signals "more", "less" are sent to electronic keys, as a result of which adjustment pulses appear at their outputs at the output of the DD9.3 element when the command is "bol", and at the output of the DD9.4 element when the command "more". These signals are sent to the +1 and -1 pins of the DD10 counter, this counter receives the "on", "off" signals, respectively, to the RE input (parallel recording, and the parallel recording inputs are connected to "+", which means on 15 of them are installed) and input R. Buffer elements DD12.3, DD12.4, DD12.5 are used to match the circuits of inputs and outputs. Signals taken from outputs 15 and 0 serve to stop the meter when reaching 15 and 0, i.e. "on" states and "off". The regulator uses a pulse method of regulation by a switching element - a thyristor. The phase regulation time determines the number of digits in the counter of the control unit and the period of the mains voltage. The data from the counter DD10 is received in the form of a digital code at the input of the parallel recording of the counter DD11. The phase information necessary for operation comes from the power supply rectifier of the entire circuit. The sinusoidal voltage from the step-down transformer T1 is rectified by a full-wave rectifier diode bridge VDS2 and fed to a variable resistor R27, and then to the input of the buffer amplifier DD1.3. With a positive half-wave at the input of the logic element DD1.3 there will be a high signal level, when passing through zero - low, and with a negative - high. As a result, the output of the element will be short negative pulses with a frequency of 100 Hz. Synchronization pulses arrive simultaneously at the input of the write permission PE of the counter DD1.1, at one of the outputs of the RS - trigger assembled on the elements DD13.3, DD13.4, and at the control input of the pulse generator (to one of the inputs of the element DD13.1). When a low-level voltage arrives at the PE input of the counter DD2, the code previously recorded on the parallel inputs D1-D4 of the counter loads it into it regardless of the signals at the clock inputs, i.e. the parallel download operation is asynchronous. In the initial position, the output 15 of the counter is high. If the count has reached its maximum, then with the arrival of the next negative clock edge at the input +1 of the counter, a level of 0 will appear at its output. In this way, low-level pulses are received at the RS input of the trigger DD13.3, DD13.4: a clock pulse from the logic element DD1.3. 11 and the output pulse of the counter DD1, shifted with respect to the clock pulse by a time determined by a digital code on the parallel inputs D4-DXNUMX of the counter. The entire circuit is powered by a stabilizer chip DA1. The circuit is set up as follows: the threshold of operation of the element DD1.3 is set so that short pulses of negative polarity are obtained at its output. Next, the master oscillator is set up, its frequency is calculated by the formula: fГ=2*FC*(2n-1), Hz, where FC is the mains frequency, Hz; n is the number of digits of the counter. Literature:
Author: Rusin Alexander Sergeevich, Moscow; Publication: N. Bolshakov, rf.atnn.ru
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