Automatic phase switch. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Clocks, timers, relays, load switches

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In the national economy, equipment powered by a three-phase network is widely used, requiring compliance with the phase sequence order. Usually this is achieved by appropriate switching of wires, but during various repairs, when additional supply cables or temporary distribution boards are used, during switching, phase sequence disturbances often occur, which can cause equipment failure.

The proposed device (Fig. 1) provides the correct phase sequence on the load with an arbitrary order of its connection to a three-phase network.

(click to enlarge)

The automatic phase switch works like this. The negative half-wave of the sinusoidal voltage of phase A passes through the VD1 diode and creates a voltage drop of about 0,7 V on it. The VU1.1 optocoupler LED does not light up, since a reverse voltage is applied to it, the optocoupler phototransistor is closed. The positive half-wave of the sinusoidal voltage of phase A passes through the LED of the VU1.1 optocoupler and makes it glow. The phototransistor of the VU1.1 optocoupler opens, and a high voltage level appears on its emitter (pin 8). The width of the pulses at the emitter practically corresponds to the duration of the half-cycle of the input signal.

The negative half-wave of phase B (C) passes through the diode VD2. the VU1.2 optocoupler LED is not lit, and therefore pin 5 is low. With a positive half-wave, the current flows through the VU1.2 LED, the transistor of this optocoupler is open, and at pin 5 VU1.2 there is a high level that goes to the clock inputs of the trigger DD2. Diodes VD1, VD2 are needed to eliminate the high reverse voltage on the LEDs of the VU1.1 and VU1.2 optocouplers.

The output signal from the VU1.1 optocoupler is fed to the information input of the upper trigger DD2 and to the integrating circuit R7-C1. Clock pulses set both flip-flops to states corresponding to the levels at their information inputs at these times. Changes in the state of triggers occur on the fronts of clock pulses (transitions 0 - 1). Thus, at the direct output (pin 1) of the upper DD2 trigger circuit, the state is "1" (high level) if the resistor R3 is connected to phase B, and "0" (low level) if it is connected to phase C. Phase , to which the resistor R1 is connected, is always taken as phase A. This information is enough to correctly connect the load to the network. The starter control circuit is shown in Fig.2.

The signals from the direct and inverse outputs of the upper trigger are fed to the inputs of the logic elements DD1.3 and DD1.4 (Fig. 1). The second inputs of these elements are connected to the direct output of the lower trigger DD2. The logic element DD1.1 together with the integrating circuit R7-C1 delays the signal for the time the device is turned on. Elements DD1.1, DD1.2 together with the capacitor C2 form a Schmitt trigger, which generates signals with steep fronts.

A low level at the output of DD1.1 appears when its inputs are "1". This happens when the voltage across the capacitor C1 exceeds half the supply voltage. With the ratings R7 and C1 indicated in the diagram, "1" appears at the information input D of the lower trigger DD2 approximately 1 s after the voltage is applied to the switch. Exposure is necessary to prevent repeated short-term switching on of the load, for example, with unreliable contacts or their sparking, which often happens with temporary connections to the network. When the network is switched off for a short time, the VU1.1 optocoupler does not work, the resistors R5 ... R7 are "0", and the capacitor C1 is quickly discharged through the resistors R6, R7. This leads to the appearance of "0" at the information input (pin 9) of the lower trigger DD2, which is transmitted to the output of the trigger (pin 13). As a result, the outputs of the elements DD1.3 and DD1.4 are set to "1". transistors VT1. VT2 are closed, and both turnips - K1 and K2 - are released. Therefore, the load is de-energized.

With the resumption of the power supply, the time delay is repeated. The R8-C3 chain sets both flip-flops to their initial state when the power is turned on. During normal operation of the switch, a low level appears only at one output of the elements DD1.3 or DD1.4. The simultaneous appearance of a low level at their outputs is excluded, because they are controlled by anti-phase signals from the upper trigger DD2.

The device is assembled on a double-sided printed circuit board, the drawing of which and the location of the elements are shown in Fig. 3 and 4.

Literature

1. A.Pankratiev. Automatic phase switch. - Radio, 2007, No. 9, P. 43.

Authors: V.Kalashnik, N.Cheremisinova, Voronezh

See other articles Section Clocks, timers, relays, load switches.

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