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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING MP3 player - set-top box for PC. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Computers The MP3 player brought to the attention of readers is a device that is an MP3 decoder connected to the parallel (LPT) port of a computer. It can be used in a stationary music center or in a car (when used to control and store information of any type of computer or device on a microcontroller), to expand the functionality of "slow" computers, etc. MP3, MPEG-1* Layer 3, MPEG Audio names of a compression technique for a digitized audio stream or file. The fundamental feature of MPEG encoding is lossy compression. After packing and unpacking an audio file using the MP3 method, the result is not identical to the original "bit for bit". On the contrary, packing deliberately excludes non-essential components from the packed signal, which leads to an extreme increase in the compression ratio. Depending on the required sound quality, the MP3 method is capable of compressing a digital audio signal by ten or more times. Thanks to this, the musical compositions of one audio CD in compressed form with acceptable sound quality occupy only 60 ... 70 MB. Today, this format is becoming more and more popular. Dozens of devices from various companies are mass-produced using a wide variety of information carriers: memory cards, CDs, hard drives. There are many amateur devices, descriptions of which, for example, can be found on the Internet [1], ranging from computers with software data decoding to devices with hardware decoding and the ability to work with several different media simultaneously. However, the use of an MP3 player with a laptop computer, even with a low-performance processor (286, 386, 486), which can be purchased on the radio market for a small fee, compares favorably with all other devices. Firstly, for the price - the cost of the microcontroller, LCD display and other parts is more than an old laptop. Secondly, in terms of functionality - a screen with a high resolution and grayscale (or even color), a large set of control keys, the ability to simultaneously use the computer for other purposes (for example, as a clock, to control various devices). Thirdly, in terms of flexibility - the software is written in a high-level programming language and can be easily and quickly changed without using a programmer using the computer itself. The block diagram of the MP3 player is shown in fig. 1. As you can see, it is connected to the parallel port of the computer and consists of a signal level converter U1, a hardware MP3 decoder U2 and a power supply A1.
The bottleneck in the device is the low bandwidth of the parallel port of the computer. When tested on a computer with an SPP (Standard Parallel Port) port based on an Intel 486DX-33 processor, the maximum data stream at which musical compositions were played without stuttering was 128 Kbps. On a computer with an EPP parallel port (improved parallel port), where the exchange rate reaches 0,5.. 2 MB / s (the exchange rate with the device is much lower, since data is exchanged only along one of the signal lines, and data strobe is performed by software ) stream of 192 Kbps and higher is normally played back. If desired, to interface the device with a computer, you can use the interface for connecting to the ISA bus, described in [2], with a slight modification of the software. However, in this case, the scope of the device will narrow - it can only be connected to desktop computers, since laptops usually do not have such a bus. The schematic diagram of the device is shown in fig. 2. The logic level converter is implemented on NOT elements with an open collector (microcircuits DD1, DD2) and transforms TTL levels into logic ones with a high level of 3 V and vice versa.
Chip DD3 (VS1001k Finnish company VLSI Oy) is a digital signal processor (Digital Signal Processor - DSP) for hardware decoding MPEG layers 1, 2 and 3 [3, 4]. Its block diagram is shown in fig. 3. The chip contains a high-performance low power DSP core (VS_DSP), working memory, program (4Kbytes) and data (0,5Kbytes) RAM for user applications, serial control and data interfaces, a high-quality DAC and a 3-frequency amplifier for head phones.
The VS1001k accepts the input data stream via the serial bus, which is connected as a slave in the system. The input stream is decoded and passed through a hybrid A/D volume control to an 18-bit delta-sigma DAC. Decoding is controlled via the serial control bus. In addition to simple decoding, you can add special applications - DSP effects, which are located in the user's RAM. To control the chip and transfer the MP3 data stream, two buses are used: SCI (Serial Control Interface) for control and SDI (Serial Data Interface) for data transfer. The purpose of the lines of these tires is given in Table 1.
VS1001k contains 15 SCI registers (Table 2). After a hardware "reset" they are all set to 0.
The MODE register is used to control the operations of the VS1001. The names of its bits, their functions and descriptions are given in Table. 3.
The STATUS register contains information about the current state of the chip. Bits 1 and 0 are used to control the analog output level (0 - 0 dB, 1 = -6 dB, 3 - -12 dB), bit 2 - to turn off the power of the analog part of the microcircuit (when it is set to one, it turns off). Writing to the VOL register (see below) automatically sets the analog output signal level and the user does not have to worry about its state. The CLOCKF register is used if the clock frequency is other than 24,576 MHz (it must be a multiple of 2 kHz). The value of this register is calculated by the formula CLOCKF = ХТ1/2000 (ХТ1 - clock frequency in hertz). The register can take values from 0 to 32767, however, larger values are limited by the maximum clock frequency of the microcircuit (32 MHz). Setting the MSB of the register to 1 enables the internal frequency doubler. The clock frequency up to 15 MHz can be doubled. The CLOCKF register must be set before MP3 data is decoded, otherwise it will not play correctly. The clock frequency determines the maximum sampling rate of audio data and the rate of the input MP3 data stream. For example, at a clock frequency of 12,288 MHz, the microcircuit decodes audio data with a sampling rate of 24 kHz and a stream of up to 96 Kbps, at a frequency of 22,580 MHz - with a sampling rate of 44,1 kHz and a stream of up to 160 kbps, a stream with a variable speed not exceeding 256 kbps. If the clock frequency is 24,576 MHz, all audio data is decoded with a sampling rate up to 48 kHz and a bit rate up to 192 Kbps, at a frequency of 28 MHz - a stream with a maximum rate of up to 320 Kbps The DECODEJTIME register, when processing the correct stream, contains the current time decoding in seconds. Bits 8-0 of the AUDATA register contain the value of the data rate in kilobits per second (if it is variable, they contain the current rate of the stream), bits 12-9 contain the sampling rate index (Table 4). Bits 14 and 13 are not used and are always set to 0. Bit 15 characterizes the type of audio data (0 - mono, 1 - stereo).
Using the WRAM WRAMADDR AIADDR registers, you can load and run user-written applications on the chip, for example, mixing channels, creating stereo effects when playing a mono signal, introducing a digital equalizer. Examples of such applications and tools for developing them can be found on the website of the chip manufacturer. However, it should be remembered that all this increases the load on the digital signal processor, and its performance is limited. For example, with a clock speed of 24,576 MHz and decoding of a 128 Kbps data stream at a sampling rate of 44,1 kHz, there is only about 28% of free processor time. When the frequency response expander is enabled (by the SM_BASS bit of the MODE register), an additional 6,5% of the DSP performance is spent. The HDAT0 and HDAT1 registers contain information about the title of the piece of music being extracted from the current MPEG data stream. The VOL register is for volume control. In each channel, the value can vary from 0 to 255 (corresponding to signal attenuation from the maximum level to zero in 0,5 dB steps). For the left channel, the value is multiplied by 256 and added to the value of the right channel. Thus, to get the maximum volume, the register must contain 0, and complete silence - 65535. After a hardware "reset", the maximum volume is set, a software "reset" does not change the set volume. When you set the minimum volume (255 in both channels), the power of the analog part is turned off, which is accompanied by a click. You can exclude it if you use the maximum value of 254 in both channels (0xFEFE) to turn off the sound. The PQ3VZ1 chip from SHARP is used in the device as a 20 V supply voltage regulator (DA51). The output voltage Uout (within 1,5 ... 20 V at a load current of up to 0,5 A) is calculated by the formula Uout = Uobr (1 + R3 / R4), where R4 = 1 kOhm, and the reference voltage Uobr = 1,25, 3 V. In this case, R1,5 \u1,25d 1 kOhm and Uout \u1,5d 1 (3,125 + XNUMX / XNUMX) \uXNUMXd XNUMX V. Filtering chokes L1-L3 and capacitors C3-C6 are used to separate the power circuits of the analog and digital parts. The microcircuit has a built-in power on / off function, which can be used in a portable version of the device. The device management software is written in C and must be compiled and placed on a computer. The author used the Borland C compiler. For control, the following functions are used, which are defined in the vs1001.h file: void SCIWrite(int aress, int data) - write to SCI; int SCIRead(int aress) - read SCI; void SDIWrite(int data) - write to SDI; void xReset(void) - hardware "reset"; int DREQ(void) - read the value of the DREQ signal. The program works like this:
If desired, set the remaining registers, for example, VOL, MODE, etc. Then the state of the DREQ output is checked by the DREQQ function. If it is set to 0 (the DREQQ function returns 0), then you can send data from an MP3 file. * The abbreviation MPEG is an abbreviation for the Moving Picture Expert Group - the name of the ISO (International Organization for Standardization) expert group, acting in the direction of developing standards for encoding and compressing video and audio data. Often the abbreviation MPEG is used to refer to standards developed by this group. In the simplest case, the program looks like this (mp3play.cpp):
When playing the next file, it is necessary to perform a software "reset" of the VS1001k chip (by setting the SMRESET bit of the SCI MODE register to 1). Checking the performance of the device begins with the analog part of the DD3 chip. On all UDDA, UDDD pins. and xRESET and TEST0 should be about +3 V, and the RCAP pin should be about +1,3 V. If the latter is 0 or UD DA, the analog part of the VS1001 is faulty. When the decoder is "hard reset" by applying a low level to the xRESET pin, the following should happen: after 4096 clock cycles after the voltage at xRESET returns to a unity level, a low level should appear on the DREQ pin, which after 6000 clock generator cycles should change to a high level . If the signal levels on this pin do not change in the order shown, the chip's internal software is faulty. Then check the operation of the SCI bus. To do this, the maximum volume value is written to the VOL register, and then the value OxFFFF, which turns off the analog part of the Vsl001k chip. As a result, a click should be heard in the headphones connected to the XS2 socket. The following program snippet (scitest.cpp) demonstrates this: five clicks will be heard at the output with a period of 0,5 s:
Now you need to check the reading of the SCI registers. To do this, write some value to the VOL register, for example 12345, and then read the information from this register and compare the result. On the computer display, if the test is successful, the message "SCI Read Test Passed" is displayed, otherwise - "SCI Read Failed" (sciread.cpp).
Next, check the record in SDI. It is convenient to use a special test built into the microcircuit that produces a sinusoidal signal at the analog output. To enable the test, it is necessary to transmit via SDI an eight-byte sequence 0x53 OxEF Ox6E n 0 0 0 0, where n = 48... 119 (selected by the user). The signal parameters are determined from the table. 5, where the sampling rate index is Fsldx = (n - 48)mod9 and the number of samples index is FSin = (n - 48)/9. For example, at n = 62 (in this case n - 48 = 14) Fsldx = 5 and FSin = 1. The value Fsldx = 5 corresponds to the sampling frequency of 16000 Hz, and the value FSin = 1-16 samples. Thus, at the output we will get a sinusoidal signal with a frequency of 16000/16 = 1000 Hz.
To exit the test mode, the byte sequence 0x45 0x78 0x69 0x74 0 0 0 0 is transmitted via SDI. The following program snippet (sinetest.cpp) demonstrates this test: on the analog output, you can listen to a signal with a frequency of 1 kHz for 5 seconds:
To test the memory of the VS1001k chip, an eight-byte sequence 0x4D OxEA 0x6D 0x54 0 0 0 0 is sent to SDI. After this command, you must wait 500 clock cycles. The test result can be read from the HDAT000 SCI register. The received data is interpreted as follows: if the bit is set to 0, then the memory test is passed (Table 1).
On the computer display, if the test is successful, the message "Memory test completed successfully" is displayed, otherwise - "Memory error xxxxx", where xxxxx is the value read from the HDATO register. Here is a fragment of the memory testing program (memtest.cpp):
To check the SCI registers, it is necessary to send the eight-byte sequence 0x53 0x70 0xEE n 0 0 0 0 to the SDI, where n is the register number for the test. The contents of the specified register are read and copied into the HDAT0 register. If it is necessary to check the HDAT0 register, then its value is copied into the HDAT1 register. The device is mounted on a printed circuit board made according to the drawing shown in Fig. 4. During installation, insert pieces of tinned wire into the holes framed by the contact pads of the minimum diameter and solder them to the printed conductors on both sides of the board. Instead of PQ20VZ51, you can use any microcircuit voltage regulator that allows you to get 3 V at the output (for example, LM317). Inductors L1-L3 any with an inductance of 10 μH. Inverters with open collector output DD1.1-DD1.6, DD2.1-DD2.3 can be K155, KR531, K555, KR1533 series. It is undesirable to replace the VS1001k chip with devices with other letter indices (previous versions), since they have a number of flaws. Literature
Author: V. Kardapolov, village Tbilisskaya, Krasnodar Territory
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