Memory devices. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Beginner radio amateur

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RAM

RAM chips are built on bipolar and MIS transistors. The memory element in the first of them is the simplest trigger, in the second - a trigger or a capacitor charged to a voltage corresponding to a single state of the element. Bipolar trigger microcircuits have a significant speed, and MIS microcircuits have a larger memory capacity. In addition, MIS microcircuits consume significantly less energy.

A typical example of trigger RAM is a parallel register. With four bits of stored information, all its components fit in one housing with 14 pins providing access to all inputs and outputs of four memory elements. The organization of memory in the form of separate registers is used when creating low-capacity RAM.

With an increase in the capacity of RAM, the problem of access to each element of memory arises with a limited number of pins in the package. This problem is solved with the help of the address organization of the memory using an address code decoder. As mentioned earlier, a decoder with n address inputs decrypts 2ⁿ states. Thus, with four inputs, it is possible to organize access to 16 memory elements with 10 to 1024 elements.

An address-type storage device consists of three main blocks: an array of memory elements (accumulator), an address fetch block (address decoder), and a control block.

Consider the purpose and interaction of these blocks using the example of a 64-bit RAM with an address sampling organization of 16 four-bit words (16 words x 4 bits = 64 bits).

A conditional image and a functional diagram of such a microcircuit are shown in Figure 1, a. The memory array is formed by 16 four-bit trigger chains. With the signal V=0, one of the chains corresponding to the set address A1-A4 goes into operation, and its signals are fed to the inputs of the AND element (7-10). With a V-1 signal, all DC outputs are low, and therefore all triggers are disabled from the drive's output busses. When V=0 and W=0, the selected chain receives information signals inputs (D0-D4) and element 1 generates a recording signal. In this mode, when information is changed at the RAM input, the information in the given word of the array is overwritten. With signals V=1 and W=0, the input information passes directly to the output of the microcircuit, bypassing the trigger array (the decoder does not select any of the circuits). And, finally, when V=1 and W=1, the operation of the decoder, the node that generates the "Record" signal, and the input elements AND is prohibited.

Fig. 1

Thus, the control unit (ten elements And) ensures the operation of the RAM in the following modes: writing, reading, end-to-end transfer, information storage.

The output AND gates are open-collector, which allows the Q outputs of several RAM chips to be connected together. In this case, the capacity of the RAM is increased - two microcircuits - 32 words, three - 48, etc.

Address control A1-A4, information inputs D1-D4 and output Q1-Q4 of all microcircuits are combined into common buses, and the choice of the working array is carried out by an additional decoder for inputs V and W. This is how the K155RU2 microcircuit is built, Figure 1,b.

Rice. 2 (click to enlarge)

When designing a RAM with a capacity of hundreds of thousands of bits in one package, it is difficult to create decoders with such a number of outputs. They were overcome when constructing matrix accumulators, in which each memory element is sampled not along one bus, but along two (by rows and columns). The functional diagram of such a RAM with a capacity of 256 bits is shown in Figure 2. Eight address inputs are required to select 256 cells. They are divided into two quadruples, each of which controls the decoder for 16 positions. For any combination of signals A1-A8, the unit values ​​of the signals on the row bus and column bus will be in only one memory element. Only this element will perceive the control signals going through the common buses: chip select CS (Chip Select), bit bus 1, bit bus 0. An analysis of the logical structure of the local control unit (three AND elements) allows you to compile a table of operating modes of this RAM.

The RAM output amplifier in the mode of recording and storing information is in the third state (state with high resistance), which allows increasing the amount of memory in the same way as for the K155RU2 chip.

The pinout of the K176RU2 and 1K561RU2 microcircuits (RAMs with such a structure are made according to the CMDP technology is shown in Figure 2, b. Using them, it must be remembered that the information on the address (A1-A8) and information inputs must change at a high level of the CS signal, as in recording mode , and in the reading mode.Otherwise, the previously recorded information will be destroyed.Change of information should be carried out at least 0,1 µs before the start of the CS=0 signal or not earlier than 0,5 µs after it ends.

ROM

Permanent memories allow only the reading of the information entered in them. The ROM contains one pre-set m-bit word for each n-bit address. Thus, ROMs are converters of the address code into a word code, i.e., a combinational system with n inputs and m outputs.

A ROM drive is usually implemented as a system of mutually perpendicular buses, at the intersections of which there is either (logical 1) or absent (logical 0) an element connecting the corresponding horizontal and vertical buses. Words are sampled in the same way as in RAM, using a decoder. The output transistors of amplifiers can be open-collector or third-state. Then, with a strobe signal V = 1, the microcircuit is disconnected from the output bus, which makes it possible to increase the memory by simply combining the outputs of the ROM microcircuits.

A huge amount of ROM, or non-volatile memory, is currently being produced, both serial and parallel types. In this article, I will only talk about parallel ROMs, since in order to talk about serial ROMs such as I². Consider a one-time programmable ROM k155re3. Its information capacity is 256 bits, the organization is 32x8. In these ROMs, the memory element is a bipolar transistor with a burnable jumper. When programming in a cell where 0 should be written, a current pulse is passed through the transistor, sufficient to destroy the jumper.

Chip K573RF6 ROM with ultraviolet erasure, memory size 64Kbit organization 8192x8. The microcircuit has a window in its housing, which is used when erasing with ultraviolet light. After erasing, this window is sealed with an opaque film. After erasing, all cells are in a logical one state. The microcircuit operates in programming mode when the power supply voltage is 25 volts, at the input -OE voltage is high. To write information, you must submit a data byte to the data outputs. Address signals and data signals are TTL level. When the address and input information is set, a programming pulse with a TTL level and a duration of 50 ms is applied to the -CE / PGM input. A programming pulse is given for each byte of information being written. After programming each cell, it is necessary to check whether it is programmed correctly. If the byte read from the ROM does not correspond to the one being written, then the programming procedure for this cell must be repeated.

Author: -=GiG=-, gig@sibmail; Publication: cxem.net

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