Frequency multiplier. Scheme, description

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Frequency multiplier. Encyclopedia of radio electronics and electrical engineering

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Encyclopedia of radio electronics and electrical engineering / Digital technology

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For lovers of digital technology, a frequency multiplier device may be of interest, at the output of which the number of pulses is a certain integer number of times greater than the input.

A diagram of such a device is shown in the figure.

(click to enlarge)

The input pulses are fed to the shaper, made on the chip DD1. Regardless of the duration of the input pulses, short high-level pulses are generated at the non-inverting output (pin 6 of the DD1 microcircuit), the duration of which is determined by the parameters of the elements C1, R1 and the built-in resistance of the microcircuit (about 2 kOhm). The period of their repetition corresponds to the period of the input pulses.

The generated short pulses are fed to two inputs (pins 2 and 3) of the counter, made on the DD2 chip, and reset it. At the four outputs of the counter (F0 - F3), the level of log.0 is set, and at the output of the element DD3.3 - the level of the log. 1 regardless of the position of switch SA1. Log.1 level on one of the inputs of the element DD3.4 (the duration of this level coincides with the duration of the period of the input pulses) allows the passage of a series of pulses through the second input from the generator on the elements DD3.1 and DD3.2. From the output of the DD3.4 element, the pulses are fed to the counting input of the D02 microcircuit (pin 14). The output pulses will stop when the level of log.3.3 is applied to the input of the element DD1. It depends on the position of switch SA1. In position 1 ("x2"), the log.1 level appears after the passage of two pulses through the counting input, i.e. the device multiplies the input pulses twice, in position 2 ("x4") - four times and in position 3 ( "x8") - eight times.

For the correct operation of the device, it is necessary to fulfill the requirement that the frequency of its own generator be at least 10 times higher than the frequency of the input pulses. At nominal

values of capacitors and resistors shown in the diagram, the generator frequency is 100 kHz, and therefore the frequency of the input pulses should not exceed 10 kHz. Due to the delay in the fronts of the input pulses during the operation of the DD1 chip, there is some delay in the output pulses compared to the input ones. The delay can be reduced by reducing the resistance of the resistor R1, but its resistance must not be reduced to a value less than 1 kΩ.

The device can use domestic radio elements K155AG1 (DD1), K155IE2 (DD2), K155LAZ (DD3), KD521A (VD1 and VD2).

Literature

Honesty multiplier. "Hobi-electronics 1", collection - Sofia, "ECOPROGRESS", 1992
Radio #9, 1997

Publication: N. Bolshakov, rf.atnn.ru

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