Frequency synthesizer TSA6060. Reference data
Encyclopedia of radio electronics and electrical engineering / Reference materials
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Philips Semiconductors is a leading manufacturer of frequency synthesizers, radio transmitter chips, receivers and other components that are used directly or indirectly in radio communication systems. Philips Semiconductors frequency synthesizers are used to build radio channel modules for car alarms, systems for collecting and processing information from remote sites, security and access control systems, and radiotelephony systems.
The TSA6060 chip [1] by Philips Semiconductors is designed to build digital synthesizers with a phase-locked loop (PLL) operating in the AM and FM bands. It includes all the elements necessary to build a frequency synthesizer with a PLL, with the exception of a voltage controlled oscillator (VCO) and a low frequency filter (LPF). The microcircuit includes: a generator and a reference frequency divider, an input frequency divider with a programmable division factor (17 bits), a digital phase detector, a two-level current amplifier and a controller for communicating with the microcontroller using the I protocol2C. The block diagram of the device is shown in fig. 1. Table 1 gives the numbers, designations and assignments of the pins of the microcircuit, in table 2 - its main technical characteristics. The microcircuit is available in DIP16 and SO16 packages, its pinout is shown in fig. 2.
Information is written to the microcircuit (its programming) is carried out along two lines - SDA and SCL - bus I2C [2]. One address and four configuration bytes are used for programming. The address byte (AB byte) contains the device address and the AS bit (Table 3). If this bit coincides with the logic level on the corresponding output of the microcircuit, configuration information is written to it. To one I2Two synths that are independent of each other can be connected to the C-bus, and the AS bit allows you to select which synthesizer you want to program. The address byte is not programmed, information is entered into it during production by the manufacturer, the contents of the AS bit are determined by the potential at pin 12 of the microcircuit.
If only part of the information needs to be updated (eg DBO+DB1), the TSA6060 can be partially programmed. In any case, the transfer must be terminated by a "stop condition". On fig. 3 shows the sequence of information transfer from the microcontroller to the frequency synthesizer. The assignment of the bits of the configuration bytes is as follows (Table 4):
- R1, R2 set the frequency grid step (Table 5);
- X determines the operating mode of the circuit ("0" - AM band, "1" - FM band);
- Y controls output keys ("0" - FM/AM key is open, AM/FM key is closed, "1" - vice versa);
- Z sets the frequency of the used quartz resonator;
- BS controls the mode of the microcircuit output of the same name (this output is open-collector), with BS="0" the output is switched to a high-impedance state, with BS="1" - in the current absorption mode;
- Т1, Т2, ТЗ determine the circuit testing modes (Table 6).
When Z="0" the microcircuit should work with a quartz resonator at 4 MHz, at Z="1" - at 8 MHz. Input frequency division factor for AM band (X="0") is S2-20 + S3-21 + S4-22 + ... + + S15-213 + S16-214, and for the FM band (X="1") SO-20 + S1-21 + S2-22 + ... + + S15-215 + S16-216.
Moreover, for AM the minimum division factor is 26=64, for FM - 28= 256.
If the CP bit (Current Amplifier Control Bit) is set to "1", then the amplifier outputs a current of about 500 µA, which provides a fast tuning speed. Otherwise (when CP="0"), the current is 25 µA, thus providing a higher tuning accuracy.
The block diagram of the PLL synthesizer is shown in fig. 4, a typical switching circuit - in fig. 5. In the synthesizer, using a phase detector, the phases of the reference frequency are compared with the frequency at the output of the programmable divider, obtained as a result of dividing the VCO frequency. When the PLL is in "capture" mode, that is, when the phase difference at the input of the phase detector is less than the limit value, the output of the current amplifier is in a high-impedance state, and the output of the loop-capture detector (INLCK) is logic "1". When the loop is out of the "capture" mode, that is, when the phase difference between the input signals is noticed by the phase detector, the current amplifier generates correction pulses for the loop filter (LPF). For the FM band, the filter is made on C5-C10-R7 elements, for AM - on C6-C9-R6. The pulse duration is proportional to the phase difference. Depending on which of the signals arriving at the phase detector is ahead of the other, the output of the current amplifier switches either to the absorption mode or to the current source mode, thereby charging or discharging the capacitors in the loop filter to the voltage necessary to put the PLL loop into the capture mode. . Outside the phase-matching mode, the INLCK output is logic "0".
Rice. 6 illustrates the sequence of the frequency control process. On the upper graph, the oscillator frequency is plotted along the vertical axis: f1 - VCO frequency, f2 - stable frequency of the exemplary oscillator. After turning on the circuit, it is first programmed. Then the frequency of the VCO begins to increase. When the phase difference between f2 and fl is less than the limit value (intervals t1-t2, t3-t4 and t > 15), the internal flag goes to "0", indicating that the circuit is in capture mode. If the frequency f1 increases slightly, the adjustment process starts, the internal flag changes to "1", and f1 returns to the capture range (interval t2-t3). If f1 decreases, everything is the same (interval t4-t5). Logic "1" at the INLCK output, indicating that f1 is in capture mode, appears with a delay equal to 8 oscillation periods of f2. This explains the absence of a logical "1" at the INLCK output during the short capture periods t1-t2 and t3-t4.
Table 1
1 |
WLCK |
PLL Loop Capture Detector Output |
2 |
XTAL |
Input for connection of a quartz resonator (4 or 8 MHz) |
3 |
Vcc1 |
Input for connecting the first power supply (for powering the digital part of the synthesizer) |
4 |
and |
Lands |
5 |
FMi |
Frequency input for FM VCO connection |
6 |
DEC |
Decoupling the prescaler |
7 |
AMi |
Frequency input for AM VCO connection |
8 |
BS |
Range control output |
9 |
Frefu |
Frequency output 40 kHz |
10 |
SDA |
Serial data input I2Off bus |
11 |
SCL |
Synchronization input I2C tires |
12 |
AS |
Chip select input |
13 |
FMO |
FM output for connecting an external filter |
14 |
LOOPi |
input for setting the output voltage amplifier |
15 |
AMO |
AM output for connecting an external filter |
16 |
Vcc2 |
Input for connecting a second power supply (for powering the analog part of the synthesizer) |
Table 2
Rated supply voltage Vcc1, V |
4,5 5,5 ... |
Rated supply voltage Vcc2, V |
(Vcc1+1)...12 |
Current consumption Icc1, mA, no more |
15 |
Current consumption Icc2, mA, no more |
1,5 |
Input frequency AMi, MHz |
0,5 30 ... |
Input frequency FMi, MHz |
30 200 ... |
Grid step Fobr, kHz |
1; 10; 25; 50 |
Input voltage AMi, mV |
30 500 ... |
Input voltage FMi, mV |
20 300 ... |
Rice. 1. Block diagram of the device
Rice. 2. Pinout of the microcircuit
Table 3
Bit number |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Bit content |
1 |
1 |
0 |
0 |
0 |
1 |
AS |
0 |
Rice. 3. The sequence of information transfer from the microcontroller to the frequency synthesizer
Table 4
Bit number |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BOD |
S6 |
S5 |
S4 |
S3 |
S2 |
S1 |
S0 |
cf. |
DB1 |
S14 |
S13 |
S12 |
S11 |
S10 |
S9 |
S3 |
S7 |
DB2 |
R1 |
R2 |
X |
Y |
Z |
BS |
S16 |
S15 |
HVZ |
- |
- |
- |
- |
T3 |
T2 |
T1 |
- |
Table 5
R1 |
R2 |
Step
exemplary
frequency, kHz |
0 |
0 |
1 |
0 |
1 |
10 |
1 |
0 |
25 |
1 |
1 |
50 |
Table 6
T3 |
T2 |
T1 |
Function |
1 |
0 |
1 |
Current amplifier in current source mode |
0 |
1 |
1 |
Current amplifier in current absorption mode |
1 |
1 |
1 |
Third state current amplifier output |
0 |
0 |
1 |
Current amplifier in absorption mode and current source |
1 |
1 |
- |
At the output BS - frequency from the divider |
1 |
0 |
- |
BS output - reference frequency |
Rice. 4. Block diagram of a PLL synthesizer
Rice. 5. Typical switching circuit
Rice. 6. Sequence of frequency control process
Publication: cxem.net
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