DVD processors ESS ES4318, ES4408, ES4408FD. Reference data
Encyclopedia of radio electronics and electrical engineering / Application of microcircuits
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Chips ES4318, ES4408, ES4408FD are the basis for building household DVD players. A high degree of integration, programmable architecture, high quality of signal processing and low cost make it possible to produce devices that meet modern quality requirements.
The microcircuits are based on a high-performance 32-bit RISC processor, which provides decoding and processing of the input data stream from the DVD drive, it also acts as a system controller. The microchip software can be expanded by connecting an external ROM. To process the decoded video signal, the microcircuits use built-in filters and converters that form a high-quality image of a given format. The variety of image recording formats makes this option particularly important (for example, to output a PAL DVD recorded in NTSC).
The output image is formed in a form suitable for use in conjunction with a wide range of PAL and NTSC decoders. Sound signals are fed to the outputs of the microcircuits in two forms - decoded (ready for direct conversion to an analog signal using a DAC) and in the form of a raw digital stream (an audio stream read from a disk). The I2S interface is used to transmit decoded audio information, and the S/PDIF interface is used to transmit the raw audio stream. These microcircuits also implement a wide range of interface functions, which include decoding remote control commands (from an IR receiver) and support for control keyboard functions. The block diagram of connecting ESS DVD-processors of the ES4xx8 series is shown in fig. 1.
Rice. 1 ES4xx8 Series ESS DVD Processor Connection Block Diagram
Chip characteristics
Chip ES4318
ES4318 DVD Processor Main Functions and Features:
- made in a 208-pin PQFP package;
- full support for decoding MPEG-1 and MPEG-2 streams;
- programmable architecture;
- disc formats: DVD-Video, Audio CD, Video CD (VCD, VCD 2.0), Super Video CD (SVCD);
- support for DVD Navigation 1.0;
- zone protection decoding (CSS).
Image processing functions:
- image format conversion "Pan & Scan" and "Letterbox";
- SmartZoom technology, which provides the ability to zoom and pan the image;
- SmartScale technology, which allows converting color television systems (for example, NTSC to PAL, etc.);
- SmartStream technology for correcting errors in reading data from a disk in real time;
- playback modes: slow-motion, fast forward, rewind, frame-by-frame and transition to a given fragment;
- support for karaoke and subtitle functions;
- on-screen display (OSD) with 16 colors, overlay function with 16 degrees of transparency;
- 8-bit component output in YUV format.
Audio processing features:
- decoding of Dolby Digital streams into a two-channel PCM stream;
- Dolby Pro Logic decoder;
- support for PCM streams up to 24 bit/96 kHz;
- simultaneous operation of digital stereo output and S/PDIF interface;
- built-in support for Sensaura Dolby Digital Virtual Surround technology;
- S/PDIF output for AC-3, DTS Digital and Linear PCM audio streams.
Interface functions:
- two interfaces for connecting a DVD drive: ATAPI or A/V bus;
- bi-directional digital serial audio interface I2S;
- direct control of the disc reader drive;
- eight multifunctional I/O ports;
- single clock signal at 27 MHz;
- support up to 2 MB SDRAM.
Chip ES4408
Most of the characteristics of the ES4408 chip are the same as those of the ES4318 chip. Unlike the previous one, the ES4408 chip has advanced sound processing functions:
- decoding Dolby Digital streams into a six-channel PCM audio stream;
- decoding MPEG multichannel streams into PCM audio stream.
In addition, the chip interface allows you to connect to it up to 4 MB of SDRAM or EDO DRAM.
The ES4408FD chip differs from the ES4408 in its built-in decoder for DTS audio streams and support for up to 8 MB of SDRAM RAM.
The pins of the microcircuits are grouped according to their functional purpose (Fig. 2):
(click to enlarge)
Rice. 2. Grouping of microcircuit pins
- 1...23 and 170...208 - built-in RISC processor interface;
- 24...52 - audio data transfer interface (I2S, S/PDIF).
- 53...104 - interface for connecting ROM and RAM;
- 105...119 - video encoder connection interface;
- 120...156 ATAPI/DCI interface for connecting a DVD drive;
- 157...169 - multifunctional input/output ports.
Circuits of the common wire of microcircuits are connected to the following pins: 8,17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98,103,112,120,129,138, 147,156,163,171,177,184,192, 200, 208.
The supply voltage is applied to the following terminals: 1, 9,18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99,104, 111,121,130,139,148,157,164, 172, 183,193,201.
Unused pins: 37, 38, 42, 202, 203.
The pin assignment of the ES4408FD chip is shown in Table. one.
Table 1
| Name |
room |
Mode |
Description |
| VCC |
1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121,130,139, 148, 157, 164, XNUM, XNUM, XNUM |
Sign In |
Supply voltage |
| LA(0-21) |
2-7, 10-16, 19-23, 204-207 |
Log out |
Address bus for the exchange interface with external devices of the embedded RISC processor |
| VSS |
8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177 |
Sign In |
common wire |
| RE5ET# |
24 |
Sign In |
Reset signal input, active low |
| TDMDX |
25 |
Log out |
TDM interface serial data line |
| RSEL |
|
Sign In |
External ROM word size selection (0 - 16 bits, 1 - 8 bits) |
| TDMDR |
28 |
Sign In |
TDM serial data receive line |
| TDMCLK |
29 |
Sign In |
TDM interface clock |
| TDMFS |
30 |
Sign In |
TDM Interface Data Block Synchronization Signal |
| TDMTSC# |
31 |
Log out |
Data enable signal, active low |
| TWS |
32 |
Log out |
Interface channel selection signal I2S (output channels) |
| SEL_PLL1 |
|
Sign In |
Input 2 for selecting the frequency of the output clock signal (see Table 2) |
| TDS(0) |
33 |
Log out |
I interface serial data line2S (channels 1 and 2) |
| SEL_PLLO |
|
Sign In |
Input 0 for selecting the frequency of the output clock signal (see Table 2) |
| TDS (1) |
36 |
Log out |
I interface serial data line2S (channels 3 and 4) |
| SEL_PLL1 |
|
Sign In |
Input 1 for selecting the frequency of the output clock signal (see Table 2) |
| TDS(2) |
37 |
Log out |
I interface serial data line2S (channels 5 and 6) |
| TDS(3) |
38 |
Log out |
I interface serial data line2S (channels 7 and 8) |
| MCLK |
39 |
Enter exit |
Clock signal for audio DACs |
| TBSK |
40 |
Enter exit |
Interface clock I2S (output channels) |
| SPDIF_DOBM |
41 |
Log out |
S/PDIF interface data output (IEC958) |
| SEL_PLL3 |
|
Sign In |
Clock input selection (0 - crystal oscillator, 1 - DCLK input) |
| RSD |
45 |
Sign In |
I interface serial data receive line2S (stereo input) |
| Rws |
46 |
Sign In |
Interface channel selection signal I2S (input channel) |
| RBCK |
47 |
Sign In |
Interface clock I2S (input channel) |
| APLLCAP |
48 |
Sign In |
External capacitor connection terminal (for frequency synthesizer) |
| XIN |
49 |
Sign In |
Conclusion for connecting a quartz resonator |
| XOUT |
50 |
Log out |
- "- |
| DMA(O-11) |
53-58,61-66 |
Log out |
Address selection signals for external DRAM |
| DCAS# |
69 |
Log out |
OAS signal (column strobe) for external dynamic RAM active low |
| DOE# |
70 |
Log out |
External DRAM access signal, active low |
| DSCK_EN |
|
Sign In |
External DRAM clock enable signal, active low |
| DWE# |
71 |
Output External RAM write signal, active low |
| DRAS(0-2)# |
72-74 |
Log out |
RAS Signals (Row Strobe) for External Dynamic RAM Active Low |
| Db(0-15) |
77-82, 85-90, 93-96 |
Enter exit |
External RAM Data Bus Signals |
| DCS(O-1)# |
97,100 |
Log out |
Chip select signals for SDRAM |
| DQM |
101 |
Log out |
RAM communication mask signal |
| DSCK |
102 |
Log out |
Clock signal for SDRAM |
| DCLK |
105 |
Sign In |
Input clock signal (frequency 27,0 MHz) |
| YUV(0-7) |
106-110,113-115 |
Log out |
YUV (8 bit) data for video encoder (picture interface) |
| PCLK2XSCN |
116 |
Enter exit |
Image Interface Clock (Doubled Screen Mode) 27,0 MHz |
| PCLKQSCN |
117 |
Enter exit |
Image Interface Clock |
| VSYNC# |
118 |
Enter exit |
Image interface frame sync, edge trigger or Fall-off output controlled by software, active low |
| HSYNC# |
119 |
Enter exit |
Image interface horizontal sync, edge trigger or Fall-off output controlled by software, active low |
| HD(0-15) |
122-128,131-137, 140,141 |
Log out |
Disc playback device (DVD drive) interface data bus |
| HCS1FX# |
152 |
Log out |
Disc player interface selection signal 1 |
| HCS3FX# |
153 |
Log out |
Disc player interface selection signal 3 |
| H1OCS16# |
151 |
Sign In |
Data request signal in 16-bit mode |
| HA(0-2) |
154,155,158 |
enter exit |
Disc player interface address bus |
| VPP |
159 |
Sign In |
Threshold protection voltage |
| HWR#/DCI_ACK |
149 |
Enter exit |
Disc player interface record signal, DCI interface acknowledge signal |
| HRD#/DQ_CiK |
150 |
Exit, exit |
Disc player interface read signal, DC1 interface clock |
| HWRQ# |
142 |
Log out |
Write request signal |
| HRDQ# |
143 |
Log out |
Read request signal |
| HIRQ |
144 |
Enter exit |
Interrupt signal |
| HRST# |
145 |
Log out |
Reset signal |
| HIORDY |
146 |
Sign In |
I/O Ready signal |
| AUX(0-7) |
160-162,165-169 |
Enter exit |
Eight software-controlled I/O lines |
| LOE# |
170 |
Log out |
Embedded RISC processor interface external device access signal, active output level - low |
| LCS(O-3)# |
173-176 |
Log out |
Output External device selection signal, active low |
| LD(15-O) |
178-182,185-191,194-197 |
Enter exit |
Data bus interface for exchange with external devices |
| LWRLL# |
198 |
Log out |
Low 16 bit write signal, active ~~ low |
| LWRHL# |
199 |
Log out |
High 16 bit write signal, active low |
| NC |
37,38,42,202,23 |
- |
Unconnected pins |
Table 2
| Output signal frequency, MHz |
Signal |
Output signal frequency, MHz |
Signal |
| SEL_PLLO |
SEL_PLL1 |
SEL_PLL2 |
SEL_PLLO |
SELPLL1 |
SEL_PLL2 |
| No |
0 |
0 |
0 |
121,5 |
0 |
0 |
1 |
| 27 |
1 |
0 |
0 |
81 |
1 |
0 |
1 |
| Equal to input signal frequency |
0 |
1 |
0 |
94 |
0 |
1 |
1 |
| 54 |
1 |
1 |
0 |
108 |
1 |
1 |
1 |
Publication: cxem.net
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