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Chips K155IE6 and K155IE7. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Application of microcircuits Microcircuits K155IE6 and K155IE7 are four-digit reversible counters, similar in structure. The IE6 counter (Fig. 1.67, a) is binary-decimal, and the IE7 counter (Fig. 1.67, b) is binary. The internal circuit of the K155IE7 counter can be studied in Fig. 1.67, c. On fig. 1.67, d shows the pinout of these counters. The pulse clock inputs for counting to increase Cu (pin 5) and to decrease Cd (pin 4) are separate in these microcircuits. The state of the counter changes on positive clock edges from low to high on each of these clock inputs.
To simplify the construction of counters with more than four digits, both microcircuits have end-of-count pins for increasing (_TSu, pin 12) and decreasing (_TSd, pin 13). From these pins are taken the carry and borrow clocks for the next and previous four-bit counter. Additional logic is not required when these counters are connected in series: the outputs _TSu and _TSd of the previous microcircuit are connected to the outputs Cu and Cd of the next one. The parallel loading enable inputs PE and reset R disable the clock sequence and give commands to load a four-bit code into the counter or reset it. In the IE6 and IE7 chips, the counters are based on four two-stage master-assistant flip-flops. The decimal counter differs from the binary one (see its diagram in Fig. 1.67, c) by the internal logic that controls the triggers. The counters can be set to reset, parallel download, and synchronous count up and down. If a low-to-high pulse edge is applied to the Cd input (down-down command is given), 1 is subtracted from the contents of the counter. A similar edge applied to the Cu input increases (up) the count by 1. If one of these inputs, on the other clock input, you should fix the voltage of a high logic level. The first counter flip-flop cannot toggle if its clock input is latched low. In order to avoid errors, the counting direction should be changed at the moments when the triggering clock pulse went high, i.e. during the flat top of the pulse. At the outputs _TSu (the end of the account for an increase, output 12) and _TSd (the end of the account for a decrease, output 13), the normal level is high. If the count has reached the maximum (number 9 for IE6 and 15 for IE7), with the arrival of the next clock edge at the input Cu from high to low (more than 9 or more than 15), a low voltage will appear at the _TCu output. After the voltage at the clock input Cu returns to a high level, the voltage at the output _TCd will remain low for another time corresponding to twice the switching delay of the TTL logic element. Similarly, a low-level voltage appears at the _TCd output if a low-level counting drop comes to the Cu input. The pulse drops from the outputs _TCu and _TCd thus serve as clocks for subsequent inputs Cu and Cd when constructing higher order counters. Such multi-stage connections of IE6 and IE7 counters are not completely synchronous, since the clock pulse is transmitted to the subsequent microcircuit with a double switching delay. If a low-level voltage is applied to the PE parallel loading enable input (pin 11), then the code previously recorded on the parallel inputs DO-D3 (pins 15, 1, 10 and 9) is loaded into the counter and appears on its outputs QO-Q3 ( pins 3, 2, 6 and 7) regardless of the signals at the clock inputs. Therefore, the parallel download operation is asynchronous. Parallel launch of triggers is prohibited if a high level voltage is applied to the reset input R (pin 14). All Q outputs will go low. If during (and after) the reset and load operations a clock edge (from H to B) comes, the microcircuit will accept it as a counting one. Counters K155IE6 (74192) and K155IE7 (74193) consume a current of 102 mA. Low-power versions of these microcircuits with Schottky junctions have a current consumption of 34 mA. Maximum clock frequency 25 MHz; the signal propagation delay time from the Cu input to the output _Tcu is 26 ns, similar delays from the PE input to the Q3 output are 40 ns. Reset signal duration (from input R to outputs Q) 35 ns. On fig. 1.68a shows a diagram of the operation of the decimal counter IE6, where the logical transitions of the signals are indicated when counting for increase and decrease. The ring count is possible within 0...9, the other six states are prohibited for triggers. The counting ring for the IE7 binary counter has no internal prohibitions (see Fig. 1.68,6).
Having made a certain combination of input signals, according to the table. 1.38 you can choose one of the four modes of operation of the counter IE6. The account for the increase here will end with the output code BHHB (9), the decrease - with HHH (0).
Similar operations with the counter IE7 allows you to carry out table. 1.39. The end of the account for the increase here corresponds to the code BBBV (15), and for the decrease - NNNH (0).
Literature: 1. V.L. Shilo. Popular digital circuits. M. Radio and communication. 1987 Publication: N. Bolshakov, rf.atnn.ru
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