Microcircuits of the LM7001 series for a frequency synthesizer. Reference data

Encyclopedia of radio electronics and electrical engineering / Reference materials

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Chips LM7001J and LM7001JM are designed to build frequency synthesizers with a PLL system used in household radio receivers. Both microcircuits are identical in circuit and parameters and differ only in the design of the case - the LM7001J has a DIP16 case for conventional mounting, the LM7001JM has an MFP20 case for surface mounting (both plastic). The housing drawings are shown in fig. 1 a and b.

The pinout of microcircuits is presented in Table. one.

Conclusions Xout and Xin - output and input of the signal amplifier of the exemplary frequency; a quartz resonator is connected to these conclusions. CE write enable signal input CL - write clock input. Data - information input SC - Syncro Control - control frequency signal output 400 kHz. BSout1 - BSout3 - band-swtching - outputs for controlling external devices (output BSout1, in addition, - signal output with a frequency of 8 Hz); These signals are used to switch ranges. AMin and FMin are the inputs of the programmable frequency divider, in other words, the inputs of the AM and FM signals. Pd1 and Pd2 - outputs of the frequency-phase detector in FM and AM modes, respectively.

The functional diagram of the device is shown in Fig.2.

The control sequence of bits arriving at the receiving shift register determines the value of the frequency grid step of the synthesizer, the division factor of the programmable frequency divider, its mode of operation and the state of the outputs BSout1 - VSoul3.

The output signal of the voltage controlled oscillator (VCO) is fed to one of the inputs - AMin or FMin. An unused input is blocked to prevent spurious noise. Frequency dividers reduce the frequency of the signals of the exemplary generator and the input signal by the required number of times - up to the value of the frequency step of the grid. The phase detector compares both signals and generates an error signal whose level is proportional to the phase difference between them. The error signal is removed from the outputs Pd1 and Pd2, depending on the selected operating mode of the microcircuit.

Main Specifications

• Rated supply voltage, V.....4,5...6,5
• High-level input voltage, V, on CE, CL, Data.....2,2...6,5 inputs
• Input voltage low level, V, inputs CE, CL, Data.....0...0.7
• The maximum allowable voltage supplied to the SC output, V ..... 6,5
• The maximum allowable voltage supplied to the inputs BSout1 - BSout3, V.....13
• Maximum allowable output current of the SC output, mA.....3
• Maximum allowable input current of inputs BSout1 - BSout3, mA.....3
• Input frequency interval AMin, MHz.....0.5...10
• Input frequency interval FMin, MHz, with a frequency grid step of 25, 50, 100 kHz.....45...13
• 1, 5, 9, 10 kHz.....5...30
• Sensitivity at the inputs AMin and FMin, V(rms).....0.1...1,5
• Typical value of the input resistance at the inputs AMin and FMin, kOhm ..... 500
• Total current consumption, mA.....40

The microcircuit can work with seven standard values ​​of the frequency grid step - 1, 5, 9, 10, 25, 50 or 100 kHz (with a reference oscillator frequency of 7200 kHz). The control sequence of bits and the main timing parameters are shown in fig. 3.

The introduction of information occurs sequentially, starting with the least significant bit of the frequency division factor of the programmable divider, which can operate in two modes - AM and FM.

In FM mode, the programmable frequency divider uses DO-D13 bits. The maximum division factor value is 3FFF (hex) or 16383 decimal.

In AM mode, bits D4-D13 are used. The maximum division factor value is 3FF or 1023.

Bits T0 and T1 are test bits and should always be set low. Bits B0-B2 and TV control the state of outputs BSout1 - BSout3; the correspondence between the states of the bits and outputs is indicated in Table. 2.

Bits R0-R2 contain information about the step of the frequency grid of the synthesizer, as well as (if the control bits B0 - B2 are set to zero) about the state of the outputs BS0Ut1 - BS0Ut3. The distribution of levels is summarized in Table. 3.

Bit S determines the operating mode of the programmable frequency divider: 1 FM, 0 - AM.

Let's consider examples of compiling a control sequence. Assume that the synthesizer is used in a VHF radio receiver with an intermediate frequency of 10,7 MHz, which receives a signal with a carrier frequency of 100 MHz. Frequency grid step - 50 kHz.

Find the required frequency division factor. If the local oscillator operates at a frequency lower than the received one, its frequency is 100 - 10,7 - 89,3 MHz. Division factor

Kdel = 89300:50 = 1786 = 6FA (hex) = 0110 1111 1010 (bin).

To convert decimal numbers to hexadecimal binary and vice versa, it is convenient to use the software calculator included in the standard programs of the Windows operating system.

If external device control is not used, the bit sequence for the microcircuit will take the form shown in Table. 4.

(click to enlarge)

When using the synthesizer in a MW radio receiver at a frequency of 1000 kHz (intermediate frequency 465 kHz), the grid step is 5 kHz. If the local oscillator operates at a frequency greater than the signal frequency - 1000 + 465 = 1465 kHz. That

Kdel = 1465:5 = 293 = 125 (hex) = 0001 0010 0101 (bin).

The control sequence for this case will correspond to Table 5.

(click to enlarge)

One of the options for a typical microcircuit switching circuit is shown in Fig. 4. Between the positive and negative power leads, it is necessary to include a blocking capacitor (C6) to reduce interference in the power circuits. Solder this capacitor as close to the chip as possible. Transition capacitors C3 and C7 between the VCO outputs and the microcircuit should also be mounted near its case.

Between each of the outputs of the frequency-phase detector and the control input of the VCOs, as a rule, an active inverting low-pass filter is included (circled in the diagram by a dashed line). The value of the filter elements is chosen depending on the required cutoff frequency and the slope of the VCOs. Filters must be carefully shielded.

The ratings of the elements in the diagram are approximate. Their value needs to be optimized based on the specific grid spacing, the required low-pass filter gain, the VCO tuning slope, etc.

Author: A. Temerev, Svetlovodsk, Kirovograd region, Ukraine

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