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Frequency divider generator KR512PS10. Reference data

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The KR512PS10 microcircuit is intended for use in timers, time relays and as a low and infra-low frequency pulse generator. The microcircuit is an RC oscillator and a controlled frequency divider with a switchable division ratio, consisting of several counters, switched by applying high-level signals to the installation inputs. The maximum value of the division factor is unique - 235 929 600. The microcircuit is manufactured using CMOS technology with self-aligned transistor gates and isolation with local oxide. Housing - plastic 2104.16-1 (Fig. 1).

Frequency divider generator KR512PS10

Weight - no more than 1,2 g.

The circuit-graphic designation of the microcircuit is shown in fig. 2.

Frequency divider generator KR512PS10

Pinout of the microcircuit: pin. 1 - signal input for setting the division ratio 26: pin. 2 - input signal for resetting counters; pin. 3 - input signal to stop counters; you. 4 - input of the amplifier-shaper; output for connecting the RC circuit of the generator; pin. 5 - direct output of the amplifier-shaper; output for connecting the generator capacitor; pin. 6 - inverted output of the amplifier-shaper; output for connecting the generator resistor; pin. 7 - free; pin. 8 - general; negative power output; pin. 9 - open-drain output of the frequency divider; pin. 10 - the usual output of the frequency divider; you. 11 - input signal to control the phase of the output signal with pin. 9; pin. 12 - signal input for setting the division factor 60; pin. 13 - signal input for setting the division factor 3; pin. 14 - signal input for setting the division factor 10; pin. 15 - signal input for setting the division factor 30; pin. 16 - positive power output.

Main technical characteristics at Tacr. Cp= -10.. .+70°C

  • Rated supply voltage, V ...... 5
  • Current consumption, μA, no more, at a supply voltage of 6 V in static mode......20
  • dynamic at a frequency of 40 kHz......1000
  • Low-level output voltage, V, not more, at a supply voltage of 4 V, measured at pins 5 and 6 (at an output current of 1.6 mA)...... 0,4
  • 9 (5,2 mA)......0,8
  • High-level output voltage, V, not less, at a supply voltage of 4 V and an output current of 1 mA, measured at pins 5 and 6 ...... 3,6
  • Low-level input current, µA, not more, at a supply voltage of 6 V, measured in the output circuit 4......0.1
  • High-level input current, µA, no more, at a supply voltage of 4 V. Measured in the terminal circuit 4 (at an input voltage of 4 V)...... 0,1
  • 1-3, 11-15(6 В)......50

Operating limits

  • Supply voltage, V ...... 4 ... 6
  • Maximum clock frequency, kHz......200
  • Ambient temperature, °С......-10...+70
  • The highest static potential, V ...... 30
  • Limit value of the power supply voltage for 10 s, V......10
  • The total operating time at the maximum supply voltage for the entire period of operation, h ...... 1

The frequency division factor of the input signal acting at pin 4 depends on the voltage levels at the installation inputs 26, 60, 3, 10. 30 (see table). If all specified inputs are logic low, the division factor is 211=2048. When a high level is applied to a yut or other installation input, the specified coefficient must be multiplied by the weight value of the input. It is permissible to apply a high level simultaneously to inputs 26, 60 and one of the inputs 3, 10, 30. If a high level is applied to two or three inputs from group 3, 10, 30, the counters will be blocked.

The IN input controls the phase of the signal at the open drain output. When this input is low, the signal at pin 9 is out of phase with the signal at pin 10, and when it is high, it is in phase.

Applying a high level to the input R0 (zeroing) sets all the frequency divider counters of the microcircuit to the zero state, corresponding to a low level at pin 10. The counters start working from the moment a low level arrives at this input. A high level at the input ST (stop) stops all counters, pin 10 retains the level that was before the "Stop" signal was given. The operation of the counters resumes at the moment when this input goes low, starting from the state in which they were stopped. The supply of these signals does not stop the operation of the clock generator.

At any division ratio, the output signal has a duty cycle of 2 ("square"). The chip contains resistors that provide a logic low on all inputs except for the RC input. when they are left free.

The structure of the chip allows you to build a clock generator with an external resistor and capacitor connected, as shown in Fig. 3.

Frequency divider generator KR512PS10

On fig. 4 - 13 shows the typical dependences of the parameters on the supply voltage, output current and frequency in the operating temperature range. The areas of parameter scatter for 95% of microcircuits are shaded. On fig. Figures 4 and 5 show the dependence of the high-level output voltage at the outputs C and R, respectively, on the supply voltage, and in fig. 6 and 7 - low level.

On fig. 8 shows the load characteristic of an open-drain output at a low level output voltage. Rice. 9 and 10 illustrate the nature of the RC input leakage current at low and high input voltage levels, respectively, on the supply voltage.

The frequency dependence of the consumed in dynamic mode is shown in fig. eleven.

Frequency divider generator KR512PS10
(click to enlarge)

Author: S. Biryukov, Moscow

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