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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Voltage polarity converter on switched capacitors. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Radio amateur designer The article considers circuit variants of a voltage polarity converter on switched capacitors using two switches instead of four. An article [1] was published in "Radio", where it is described in detail the principles of operation of these converters, built on four analog switches. The possibilities of implementing such converters on two switches are shown below.
The principle of operation of the converter on two electronic switches is explained by the diagram in fig. 1. Switches S1 and S2 are controlled by two anti-phase signals. When the "contacts" of the switch S1 are closed (and S2 are open), the capacitor C1 is charged from the power source through the diode VD2 almost to the level Upit (we neglect the voltage drop Upr.d on the open diode VD2). Then, when the "contacts" of the switch S1 open and S2 close, the capacitor C1 is connected to the capacitor C2 through the diode VD1. As a result, it is discharged to the capacitor C2. The voltage across capacitor C2 will increase to
and after several switching it will reach the steady value |-UBblx| ≈ Upit-2Upr.d, if we neglect the value of the resistance rn of the serial discharge circuit. Thus, the output voltage of the negative side of the converter will always be less than the positive one. A practical circuit of the switch is shown in fig. 2. The converter is assembled on two analog switches DA1.1, DA1.2. Opposite-phase control signals are fed to the inputs of the DE switches. When the switch DA1.1 is closed, the capacitor C1 is charged through the diode VD1, which then, after opening the switch DA1.1 and closing DA1.2, is discharged through the diode VD2 to the capacitor C2, etc. The load characteristic of the converter under equal conditions is almost the same as that of prototype. It should be noted that in order to ensure a rigid load characteristic, the capacitance of capacitors C1 and C2 must be chosen in a certain way. The fact is that the negative arm of the load is powered by the discharge current of the capacitor C2. In steady state, at the stages when the switch DA1.2 is open and there is no energy supply to the capacitor C2, the decrease in voltage -Uout should not go beyond the amplitude of the variable voltage component (ripple ΔU) allowed for the load, usually no more than 1 ... 2% of Uout). Therefore, with a duty cycle of the control signals equal to 2 and a switching frequency f, the value of the capacitance of the capacitor C2 must satisfy the condition
The value of the capacitance of the capacitor C1 should be such that at the stage of the closed state of the switch DA1.2 not only provide the required load current with a simultaneous increase in voltage |-Uout| by ΔU lost during the previous stage, but also to compensate for voltage losses at the open p-n junctions of the diodes VD1 and VD2 and the active resistance rn of the series capacitor C2 charging circuit. Obviously, the capacitance of the capacitor C1 must be greater than the capacitance of the capacitor C2. Since the relative proportion of losses on the diodes VD1, VD2 and series resistance rn is the greater, the lower the output or supply voltage, then in practice it is desirable to choose the capacitance of the capacitor C1 at least 2 and 1,3 times the capacitance of the capacitor C2 at voltage Upit, equal to 5 and 15 V, respectively. Low-power low-voltage Schottky diodes are best suited for the converter, especially at low values of Uout. This is also true for other types of transducer discussed below. It should also be taken into account that at Upit > 5...6 V there is a danger of current overloads through the switches at the very beginning of the starting process. To attenuate overloads, an additional current-limiting resistor R1 should be connected in series with capacitor C1 (shown in Fig. 2 by a dashed line). For example, when Upit = 15 V, the permissible current through the switch is 20 mA and the resistance of the closed switch is 100 Ohm, the value of the resistor R1 is in the range of 300 ... 400 Ohm. In this case, the capacitance of the capacitor C1 should be increased to a value of 1,5C2. The current capabilities of the converter can be significantly improved if two complementary transistors included in the push-pull stage are used as switches S1 and S2 (Fig. 3). Here, the value of rn is very small and the losses on it can be neglected, and the allowable current of transistors is much higher than that of analog switches. The transistors of this converter are controlled by one common signal in antiphase. If the generator of this signal is assembled on TTL or CMOS microcircuits, the current capabilities of the transistor VT1 cannot be fully used due to the fact that the allowable high-level output current of these microcircuits (outflowing), as a rule, is significantly less than the low-level current (inflowing). However, such a drawback can be easily eliminated by using both transistors of the pn-p structure, and feeding their base circuit with two control pulse sequences shifted in phase by 180 degrees. In this case, two basic current-limiting resistors of the same resistance will be required. The value of these resistors is determined taking into account the voltage Upit, the maximum allowable collector current (Ikmax) and the static current transfer coefficient of the base h21e. Moreover, for the circuit in Fig. 3, it is necessary to additionally take into account the value of the permissible outflowing current of the control signal generator. The correct value of the base resistors eliminates the possibility of current overload of transistors (especially during start-up), as well as the control signal generator (in all modes). This is the advantage of transistor-based converters compared to those assembled on analog switches (see Fig. 2), where overcurrent protection is achieved by worsening the load characteristic by introducing a current-limiting resistor R1. Now, when the current through both p-n-p transistors is limited, when determining the maximum allowable load current lH max, it is possible to operate with the maximum current through these transistors:
In addition, due to the ability of switching transistors to operate in saturation mode, it is possible to neglect the losses of the discharge circuit and express the output voltage with a more accurate ratio: |-Uout| = Upit - 2Upr.d. The current capabilities of the converter on complementary transistors (Fig. 3) can be significantly increased if the analog timer KR1006VI1 is used as a control pulse generator according to one of the schemes in [2]. You can also amplify the current control signal with an emitter follower on an npn transistor. Then the load characteristic of this converter will be the same as that of the one assembled on pnp transistors. The most interesting, in my opinion, is the option of building a converter on the timer KR1006VI1 (Fig. 4), which performs the functions of both switches. The timer is switched on according to the Schmitt trigger circuit [2]. One of the timer outputs - pin 3 - allows the inflowing and outflowing current up to 100 mA (200 mA per pulse). To control the timer, one sequence of low-power pulses is required, applied to the combined inputs R and S; no current-limiting resistor is required.
Thanks to the introduction of the polarity of two diodes into the converter, it becomes possible to build an even simpler converter - with just one transistor (Fig. 5). The prototype here is the node according to the diagram in Fig. 1, where switch S1 is replaced by resistor R1, and S2 is replaced by transistor VT1. When the transistor is closed, capacitor C1 is charged through resistor R1 and diode VD1, and as soon as the transistor opens, this capacitor is discharged through diode VD2 to capacitor C2. Due to simplicity, its current capabilities are also very modest due to low efficiency. When the transistor VT1 is open, along with the discharge current of the capacitor C1, a useless current also flows from the power source, equal to Upit / R1 and much larger than the load current. However, if efficiency is not one of the critical factors, this converter can be used in low-power power supplies with an output current of up to several milliamps. A few words about the optimal operating frequency of the considered polarity converters. From the above formula for capacitance C2, it follows that a higher frequency corresponds to a lower capacitance necessary to provide the required output current. The limiting frequency here is largely determined by the frequency characteristics of the elements, primarily capacitors and switches. Optimal for devices according to the scheme in Fig. 3 and 4, where, based on the possibility of obtaining relatively large values of the load current, oxide capacitors can be used, the frequency should be considered within 10 ... 20 kHz. And in less powerful switch converters on analog switches, the frequency can be increased to almost 100 kHz using miniature high-frequency capacitors. The upper frequency limit of converters with a switch on two transistors is also limited by the fact that due to the difference in the values of their on and off times, a through current inevitably appears, the dynamic losses from which increase sharply with increasing frequency. Therefore, a decrease in the capacitance of capacitors C1 and C2 with increasing frequency and the transition to non-oxide capacitors do not always give a positive effect. However, the main obstacle to increasing the current capabilities to the nominal current value of the applied switches is, of course, the series resistance rn of the charging and discharging circuits. I believe that because of it, there is a sharp drop in the output voltage of converters on analog switches (especially with four switches, as in [1]) at current values that are significantly lower than the switches themselves allow. In this regard, the converters in the circuit in fig. 3 and 4 compare favorably with almost ten times lower resistance rn. In conclusion, we note that in cases where the duty cycle Q of the control pulses is more than two, the calculated value of the capacitance of capacitors C1 and C2 should be increased by a factor of 0,5Q. Literature
Author: E. Muradkhanyan, Yerevan, Armenia
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