Frequency dividers with a meander at the output. Encyclopedia of radio electronics and electrical engineering

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The combination of the conditions "odd division factor and "meander" at the output of the frequency divider" requires the use of special circuit solutions. Some of them have already been described on the pages of the magazine "Radio". In the selection published here, we introduce readers to simpler solutions to this problem.

Everything said in [1] regarding the division of the frequency by three while maintaining the "meander" at the output remains valid for any other odd division ratio. At the same time, with a small numerical value of this coefficient, a significant simplification of the frequency divider is possible.

The frequency dividers described here by three and by five are close in speed to the microcircuits used. The dividers are operable at any initial state of the flip-flops, so further, for definiteness, we assume that when the power is turned on, the flip-flops will be in the zero state.

The circuit of a frequency divider by three, built on two D-flip-flops, is shown in fig. 1, and the signal diagrams explaining its operation are shown in Fig. 2.

The front of the first input pulse will transfer to state 1 trigger DD1.1. With the arrival of the second pulse in state 1, the trigger DDI.2 will also switch.

After the decay of the second pulse, both inputs of the DD2.1 element will be low, so the low level from the output of the element will return the trigger DD1.1 to state 0. The edge of the third input pulse will return the trigger DD0 to state 1.2. The state of the trigger DD1.1 will not change, because during the positive edge of the input signal, the trigger remains blocked by a low level from the output of the element DD2.1.

By the arrival of the fourth input pulse, the divider will be in its original state.

Instead of the OR element DD2.1, it is permissible to use the more common AND-NOT. A diagram of such a variant of constructing a divider is shown in Fig. 3. The device practically does not differ from the original one (signal diagrams correspond to Fig. 2). To disable the operation of both dividers, it is enough to apply a low level to the S input of any of the flip-flops.

A similar connection of flip-flops with feedback is applicable for building a frequency divider with other odd division ratios (2). On fig. 4 shows a circuit of a divider by five (signal diagrams - in Fig. 5).

The first three input pulses will alternately transfer the device triggers to state 1. After the decay of the third pulse, the low level from the output of element DD4.1 will return trigger DD0 to state 1.1. With the arrival of the fourth pulse, the output of the element DD2.1 will be low and the trigger DD1.2 will go to state 0. The trigger DD3.1 will also take the same state under the action of the fifth counting pulse. Then the cycle of work is repeated.

All the described devices retain the duty cycle of the input pulses if it is equal to 2. Otherwise, the duty cycle Qout of the output pulses will be equal to:

Qout=3Qin(1+Qin) and 50in/(1+2CM for dividers by three and five, respectively (Qin is the duty cycle of the input signal).

This circuitry approach is applicable to create dividers with a large division factor. But this can hardly be considered appropriate due to the rapidly growing number of required microcircuits. The frequency divider by seven or more should be built according to the recommendations given in [1].

Literature

1. Shitov A. Frequency divider by three with "meander" at the output. - Radio, 1996. No. 7. With. 51.52.
2. Goroshkov B. I. Elements of radio electronic devices. - M.: Radio and communication, 1989, p. 136.

Author: A. Shitov, Ivanovo; Radio #2 1998

Addition

In his article "Frequency divider by three with a "meander" at the output" ("Radio", 1996, No. 7, pp. 51, 52), A. Shitov described two variants of the divider by three, preserving the "meander" at the output. Note that in the first of them, elements of three microcircuits (cases) are used, in the second - four. Such "wastefulness" is not always justified.

I propose a variant of the same divider (its block diagram is shown in Fig. 7 in A. Ivanov's article "Use of the EXCLUSIVE OR element" ("Radio", 1985, No. 2, p. 37), but more economical. It uses "semi- case" of one microcircuit and a quarter of another. The divider circuit is shown in Fig. 1, and the timing diagrams of its operation are shown in Fig. 2.

Up to the moment t1 (and taking into account the delays - up to t2) at the output 2 of the counter DD2.1 there is a low signal, the element DD1.1 repeats the input sequence. At the moment t2, a high level appears at the output 1 of the counter (diagram 4). element DD1.1 EXCLUSIVE OR becomes an inverter and from the moment t2 to t6 transmits the input sequence (diagram 1) with inversion, and from t6 to t10 - again without inversion, etc.

Thus, due to the supply of a signal from output 1.1 of the counter to the lower input of the DD2 element according to the circuit, the element periodically inverts the input sequence (diagram 2) and during a time interval containing three periods of the input frequency, for example, from t1 to t9, for every three fronts of the same name of the input sequence (diagram 1, moments t1, t4, t7) generates four fronts of the same name (diagram 2, times t1, t3, t5, t7), which, acting on the frequency divider by 4, ensure the fulfillment of the dependence Fout = Fin / 3 (diagram 4).

In the described divider, a signal with a frequency of 1.1Fin / 4 can be removed from the output of the DD3 element, but the period of this sequence consists of two pulses of unequal duration (pauses are the same; diagram 2). In addition, from the output 1 of the counter DD2.1, you can get a signal with a frequency of 2Fvx / 3 and a duty cycle of 3.

Instead of counter DD2.1. used as a frequency divider by 4, if necessary, another divider by 4 is suitable, made, for example, on another binary counter or on two K561TM2 triggers connected in series in counting mode.

To shift the output "meander" by half a period of the input frequency, it is enough to apply the output signal of the element DD1.1 to the input CP of the counter DD2.1. and connect its CN input to a common wire.

The divider also allows you to implement division ratios of 7 or 15 while maintaining the duty cycle of the output signal equal to 2. To do this, just switch the lower input of the DD1.1 element according to the circuit to output 4 or 8 of the counter, respectively. From these outputs, the output signal of the divider is also taken.

Check the performance of the divider using an oscilloscope or frequency meter. To obtain a stable image on the oscilloscope screen, it is better to synchronize it with an external signal from one of the highest bits of the DD2.1 counter (from output 4 or 8). The waveform should be close to that shown in fig. 2. The pulse of diagram 2 between the moments t1 and t2 is very narrow, and in order to see it, you can try to defocus the oscilloscope beam.

When checking with a frequency meter, measure the frequency at points 1 - 4 of the divider and make sure that the measured values ​​correspond to those indicated on the diagram.

Author: A.Samoilenko, Klin, Moscow region, Ivanovo

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