Harmonic signal generator with crystal oscillator stability. Scheme, description

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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING
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Harmonic signal generator with crystal oscillator stability. Encyclopedia of radio electronics and electrical engineering

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Encyclopedia of radio electronics and electrical engineering / Radio amateur designer

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This article explains how to obtain a high-precision sine wave signal with low frequency drift by synthesizing a sine wave from a digital signal source. This stable, high-precision sine wave signal is ideal for servo drives, instrumentation, and telecommunications applications.

Servo drives, instrumentation, and telecommunications systems require a stable, high-precision sine wave source to operate. There are many different harmonic generator circuits, but finding a circuit with satisfactory signal quality and high frequency stability is a challenge.

But if you synthesize a sinusoidal signal from a digital one, you can get a sinusoid with low drift and a high-quality signal. Since the square wave includes the fundamental plus an infinite number of odd harmonics, you can get a sine wave at the frequency of the fundamental by removing the harmonics with a low pass filter. A switched capacitor filter is suitable for this (Fig. 1). IC3 is an 8th order Butterworth LPF.

Harmonic signal generator with crystal oscillator stability
Rice. 1. Filtering the harmonics of a square wave allows you to get a sine wave at the output with frequency stability like a crystal oscillator

A signal from a crystal oscillator with a frequency of 8 MHz is fed to a divider by 8, and the resulting frequency of 1 MHz is then fed to capacitor C1. (The 2MHz and 500kHz signals from the output of IC1 can be used to generate a sine wave at other frequencies.) Transistor Q1 converts the 1 MHz signal level to the level necessary for counter IC2A to operate. (To obtain a single polarity output signal, you can use a unipolar voltage source by applying half the supply voltage to the common pin of IC3 and adding a decoupling capacitor). Synchronous counter IC2 divides 1 MHz by 256, giving an output of 3906 Hz, and IC3 filters the harmonics.

The filter clock is taken from the first divider by two of IC2 to give a signal with a 50% duty cycle. IC2 divides this signal further by 128 to bring the 1MHz/256 filter input into the flat portion of its frequency response. The 50% duty cycle at the output of IC2 provides a symmetrical sine wave at the output of the filter. The filter's main pole, or corner frequency, is constant relative to the clock frequency and is in a ratio of 100:1 to it. The filter reduces the amplitude of the lower harmonics to a level of -80 dB.

Since the filter input frequency and the clock frequency are in a ratio of 1:128, a change in the frequency applied to the capacitor C1 will proportionally change the frequency of the harmonic signal at the output. Changing this frequency, for example in the range from 2 MHz to 500 kHz, will change the input frequency in the range from 7812 Hz to 1953 Hz. In this case, the amplitude of the output signal does not change, since the operating range lies much lower than the angular frequency of 25 kHz. The aliasing effect is also not a problem, since those frequencies that represent a potential cause of aliasing in this circuit are odd harmonics, with frequencies above half the sampling frequency having negligible amplitudes.

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