Universal digital scale. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Digital technology

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When developing this device, the authors set themselves the task of obtaining high speed, minimal interference with radio reception, low power consumption, and also achieving universality in application, i.e. the possibility of flexible adjustment of the operating mode.

The described digital scale is three-input, it allows you to measure the signal frequency in the range of 0 ... 01 MHz, resolution - 30 kHz, measurement time - 0,1 s. The input signal level can be in the range of 0,5 ... 0,25 V. The input resistance is 1,5 kOhm. The node consumes a current of 8,2 mA from a 15 V power supply.

A feature of the device is the possibility of its operation in several modes in accordance with the principle of forming the tuning frequency of the receiver or transceiver. The operation algorithm of the digital scale depends on the binary code on the control inputs So, Si. The indicator readings are determined by the frequencies fi, fa, fs of local oscillators, the signals of which are fed to the inputs in accordance with the table.

The device can be used without modifications in transceivers with one or two frequency conversions. In addition, it can be used as a frequency counter. In this case, the measured signal can be applied to any "summing" input.

The schematic diagram of the digital scale is shown in fig. 1. The scale consists of an input multiplexer DD1, a pulse shaper in TTL levels on transistors VT1-VT3, a high-speed frequency divider by 16 on triggers DD2, DD3, a six-decade reversible counter (DD10-DD15), a register with a decoder of a binary-decimal code into a seven-segment code indicator (DD16-DD21), digital indicators - HG1-HG6, crystal oscillator on the elements DD4.1, DD4.2 and control unit (DD5-DD9).

Input signals with frequencies f1, f2, f3 alternately pass through the pulse shaper, frequency divider and are fed to the input of the counter. Depending on the combination of external signals received at the inputs S1, S0 of the control unit, the counter is set to the addition or subtraction mode in accordance with the above table of operation modes.

The control device determines the sequence of input signals, generates counting pulses of the required duration, setting the counter to zero and writing the counting result to a register with a decoder. The operation of the entire device is synchronized with pulses generated by a quartz oscillator. From its output, they are fed through the controlled frequency divider DD6-DD8 to the input of the EC command counter DD9. The total division factor of counters DD6.1, DD6.2 is 64. The conversion factor of microcircuits DD7, DD8 is 10 if their inputs D1-D4 have a low logic level, and 250 if they are high.

We will consider the interaction of nodes from the moment when a pulse appears at the output 0 of the counter DD9, allowing the preliminary recording of the initial code in the reversible counters DD10-DD15. The next pulse that came to the input of the EC counter DD9 will cause a high logic level to appear at output 1, which is fed to the inputs of the preset counter DD8, as a result of which the frequency conversion factor of the quartz oscillator becomes equal to 16000. Under the action of this signal, the first key also opens (between the outputs 1 and 2) of the multiplexer DD1 and a signal with a frequency f1 passes into the measuring channel.

Counters DD10-DD15 when measuring the frequency f1 operate in the summation mode, since their inputs ±1, regardless of the control signals at the inputs S0, S1, a high logic level is supplied from the output of element DD5.4. When low, the six-decade up/down counter operates in subtraction mode.

After 16 cycles of the crystal oscillator (after 000 ms), a pulse will appear at output 160 of the command counter DD2. This will complete the counting of the input signal with frequency f9.

The number of pulses received by the counter during the measurement is Ni=(f1/16)t1=0,01f1, where t1 is the counting time equal to 160 ms.

In state "2" of the command counter DD9, a pause is formed during which counting is disabled, the frequency divider in the measuring channel is set to its original - zero - state, and the input of the pulse shaper is connected to the common wire through capacitor C4. The pause duration is 6,4 ms, since during the pause the frequency division factor of the DD7, DD8 microcircuits is 10.

After the end of the pause, the program counter will go to state "3". In this case, a signal with a frequency f2 enters the measuring channel. At the same time, the reverse control unit generates a counting direction signal (logical 1 - summation, 0 - subtraction) depending on the control signals S0, S1. The counting of the signal with frequency f2 also lasts 160 ms. By the end of the count, the number of pulses counted by the counter will increase or decrease by 0,01f2. At the end of the count, a pause will be generated (team counter in state "4"). Similar processes occur when studying a signal with a frequency f3, after which another pause occurs.

In state "7" counter DD9 is formed by the last cycle command. According to her information from the counters. DD10-DD15 is written to the register with a decoder (DD16-DD21) and displayed by indicators HG1-HG6. Then the cycle of commands will repeat. The measurement period is determined by the total duration of all commands and is equal to 505,6 ms.

High speed (30 MHz) is obtained through the use of a high-speed frequency divider based on TTLS triggers DD2, DD3. Docking in terms of signal levels of TTLSh and CMOS microcircuits was obtained using an unusual way of powering TTLSh triggers. Power is supplied to these microcircuits from the terminals of the VD1 zener diode, the anode of which is connected to a common wire through the VD2 zener diode. As a result, the signal levels at the output of the frequency divider are 6,8 (logical 0) and 10,8 (logical 1) V. These levels are located symmetrically with respect to the switching voltage of the counters DD10-DD15, which ensures the normal operation of the device.

Static result indication and CMOS elements ensure low radio interference emission and acceptable indicator brightness at the selected supply voltage (15 V). Setting up the device comes down to setting the frequency of the crystal oscillator by selecting capacitor C6, since the accuracy of the scale depends on the accuracy of setting the frequency of the crystal oscillator. In the absence of an account, it may be necessary to replace the zener diode 'VD2 - KS168A with KS162A or KS156A if the switching voltage of the counters DD10-DD15 is lower.

Digital scale mounted on two printed circuit boards (fig. 2), (fig. 3), (fig. 4), and one of them contains only microcircuits. The boards are located in the case one above the other. A quartz resonator at 200 or 400 kHz can also be used in the device. In these cases, pin 10 of the DD6 chip is connected to pin 5 or 6, and not 4, respectively. Diodes VD3-VD9 are any high-frequency. Instead of K176ID2 decoders, you can use K176IDZ.

When installing the device in the transceiver, the signals to the scale inputs must be applied via short shielded wires. The control signals to the inputs S0, S1 are removed from the range switch, while the logic 1 level must be within 11 ... 15 V, O - 0 ... 5 V.

Authors:V. Buravlev, S. Vartazaryan (UA6LD), V. Kolomiytsev; Publication: N. Bolshakov, rf.atnn.ru

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