triggers. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Beginner radio amateur

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A trigger is a serial type device with two stable equilibrium states, designed to record and store information. Under the action of input signals, the trigger can switch from one stable state to another. In this case, the voltage at its output changes abruptly.

As a rule, the flip-flop has two outputs: direct and inverse. The number of inputs depends on the structure and functions performed by the trigger. According to the method of recording information, triggers are divided into asynchronous and synchronized (clocked). In asynchronous triggers, information can be recorded continuously and is determined by the information signals acting on the inputs at a given time. If information is entered into the trigger only at the time of the action of the so-called synchronizing signal, then such a trigger is called synchronized or clocked. In addition to information inputs, clocked triggers have a clock input, a synchronization input. In digital technology, the following designations for trigger inputs are accepted:

• S - separate input of the installation in a single state (high-level voltage at the direct output Q);
• R - separate input of setting to the zero state (low level voltage at the direct output Q);
• D - information input (information intended for entering into the trigger is supplied to it);
• C - synchronization input;
• T - counting input.

The most widely used in digital devices are an RS flip-flop with two installation inputs, a clocked D-flip-flop and a counting T-flip-flop. Consider the functionality of each of them.

Asynchronous RS trigger. Depending on the logical structure, RS-flip-flops with direct and inverse inputs are distinguished. Their schemes and symbols are shown in the figure. Triggers of this type are built on two logical elements 2OR-NOT - a trigger with direct inputs (a), 2I-NOT - a trigger with inverse inputs (b).

Rice. 1 (click to enlarge)

The output of each element is connected to one of the outputs of the other element. Here are the truth tables for each of these triggers.

In tables (Q^t and -Q^t denote the levels that were at the outputs of the trigger before the so-called active levels were applied to its inputs. Active. call the logical level acting at the input of the logical element and uniquely determining the logical level of the output signal (independent of the logical levels acting on the other inputs). For NOR-NOT elements, a high level is taken as the active level, and for NAND elements, a low level is taken. Levels, the supply of which to one of the inputs does not lead to a change in the logic level at the output of the element, is called passive. Q levels^{t + 1} and -Q^{t + 1} designate logical levels at the outputs of the Trigger after the information is fed to its inputs.

For flip-flop with direct Q inputs^{t + 1}=1 at S=1 and R=0; Q^{t + 1}=0 at S=0 and R=1; Qt+1= Qt for S=0 and R=0. With R=S=1, the trigger state will be indefinite, since during the action of information signals, the Logic levels at the trigger outputs are the same (Q^{t + 1}=-Q^{t + 1}=0), and after the end of their action, the trigger can assume any of the stable states with equal probability. Therefore, such a combination is prohibited (and may disable the trigger).

Mode S=1, R=0 is called recording mode 1 (because Q^{t + 1}=1); mode S=0 and R=1 - write mode 0. Mode S=0, R=O is called the information storage mode, since the output information remains unchanged. For a flip-flop with inverted inputs, the logical 1 recording mode is implemented when -S=0, -R=1, the logical 0 recording mode - when -S=1, -R=0. At -S=-R=1 information storage is provided. The combination S=R=0 is prohibited.

However, it should be noted that RS flip-flops are practically not used in digital devices due to their low noise immunity.

Clocked D flip-flop. It has an information output and a synchronization input. One of the possible block diagrams of a single-cycle D-flip-flop and its symbol are shown in the figure.

Fig. 2

If the signal level at the input C= 0, the trigger state is stable and does not depend on the signal level at the information input. At the same time, passive levels (-S=-R=3) are fed to the inputs of the RS flip-flop with inverse inputs (elements 4 and 1). When applied to the synchronization input of level C=1, the information at the direct output will repeat the information supplied to the input D. Thus, at C=0 Q^{t + 1}=Q^t, C=1 Q^{t + 1}=D). The truth table of a clocked D-trigger looks like this:

Here Q^t means the logic level at the direct output before the clock pulse is applied, and Q^{t + 1} - logic level at this output after the synchronization pulse is applied.

Figure 3 shows the timing diagrams of a clocked D-flip-flop. In such a trigger, the output signal is delayed relative to the input signal. pause time between clock signals. For the stable operation of the trigger, it is necessary that the information at the input be unchanged during the clock pulse.

Clocked D-flip-flops can be with potential and dynamic control. For the first of them, information is recorded during the time at which the signal level C=1. In flip-flops with dynamic control, information is recorded only during the voltage drop at the synchronization input. Dynamic inputs are depicted in the diagrams as a triangle. If the top of the triangle is facing the microcircuit, then the trigger is triggered by the front of the input pulse, if from it - by the cut. Even in the diagrams you will find / and \ designations for the first, respectively, the front, the second decline. In such a trigger, the input information can be delayed by one cycle in relation to the input information.

Fig. 3

Counting T-flip-flop figure 4, a. It is also called a flip-flop with a count input. It has one control input T and two outputs Q and -Q. Information at the output of such a trigger changes its sign to the opposite with each positive (or each negative) voltage drop at the input. A trigger of this type can be created on the basis of a clocked D-trigger if its inverse output is connected to an information input (Fig. 4b). As can be seen from the diagram in Figure 4, c, the frequency of the signal at the output of the T-flip-flop is two times lower than the frequency of the signal at the input, so this trigger can be used as a frequency divider and a binary counter. In the series of microcircuits produced, there are also universal JK flip-flops. With the appropriate connection of the input logic, the JK flip-flop can perform the functions of any other type of flip-flop.

Author: -=GiG=-, gig@sibmail; Publication: cxem.net

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