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Calculation of bit synchronization of the CAN network. Encyclopedia of radio electronics and electrical engineering

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When using the CAN interface, a big problem is related to setting the speed of transmission and reception of information in the CAN module of the microcontroller. The article describes the general principles of this installation according to the Bosch specification. As an example, the basic formulas for calculating the values ​​of parameters written to the control registers of the CAN modules of ARM LPC23xx and STM32F103 microcontrollers are given, and a program developed by the author that helps to choose the best option is considered.

The CAN (controller area network) interface got its start in the mid-80s of the last century from the German company Robert Bosch Gmbh, which created it as an economical means for integrating controllers that control vehicle systems into an information network. The fact is that as automotive technology improved, so did the electronics that control the engine, gearbox and other mechanisms. This led to the fact that dozens of wires from sensors and actuators, as well as wires connecting different blocks to each other, began to stretch to each electronic unit in the car. All this not only made the car heavier, but also affected its reliability, safety, and maintainability.

As this interface spread, similar networks began to be used in other areas, in particular, for the automation of technological processes. The high reliability of information protection against distortion when working in harsh conditions and a sufficiently high transmission rate (up to 1 Mbps) made it possible to use cAn in places other than its original purpose. The reliability of the network is ensured by the presence of developed mechanisms for detecting and correcting errors, self-isolation of faulty nodes, and insensitivity to a high level of electromagnetic interference.

The CAN ideology is based on the seven-level OSI / ISO model (in simple terms, this is a virtual division of the processes of transmitting and receiving information into seven levels). It makes no sense to delve into this area, since it is widely covered in many sources, for example, in [1]. Currently, two levels are standardized: physical (partially) and channel.

The physical transmission medium is not defined in the Bosch CAN specification, but is generally understood to be a bus-type network with a physical layer in the form of a pair of wires according to the ISO 11898 standard. Connection types and transmission speed are not currently standardized, but they are usually specified in the specifications of the overlying layers.

All network nodes are connected to two wires of the line connecting them (CAN_H and CAN_L) in parallel. At the ends of the communication line, terminators must be installed - resistors with a resistance of 120 ohms. In the absence of transmission, the voltage on both wires relative to the car body or the common wire of the technological installation is 2,5 V. A logical unit (according to the terminology adopted in CAN, a bit with such a value is called recessive) corresponds to a bus state in which the voltage level on the CaN_H wire is higher than on CAN_L. Logical zero (a bit with such a value is called dominant) - vice versa. When several transmitters operate simultaneously, the recessive bit in the line is suppressed by the dominant bit.

It is assumed that the passive state of the bus corresponds to the level of logical one. It is in it when no messages are transmitted. Message transmission always starts with the dominant bit. The bus wires in the CAN module of each node are connected to a special chip - a bus driver that performs the functions of a transceiver. In addition, the driver may provide some additional features:

- regulation of the signal slew rate by changing the input current;
- protection of the transmitter outputs from damage in case of possible short circuits of the CAN_H and CAN_L wires with power circuits using the built-in current limiting unit, as well as from a short-term increase in voltage on these wires;
- internal thermal protection;
- low power mode, in which the receiver continues to report the status of the bus to the controller so that when it detects its activity, it can transfer the driver to normal operation.

Encoding of information for transmission over the bus is carried out using the NRZ (Non Return to Zero) method. It has a significant drawback: when transmitting a long sequence of units, it turns out that there are no pauses between them. This results in the receiver not being able to distinguish between such a sequence and a pause between messages. To solve this problem, the so-called bitstaffing (Bit Stuffing - bit stuffing) is used. It consists in the fact that after five identical bits transmitted in a row, an additional bit with the opposite value is inserted into their stream. The receiver, having found five identical bits in a row, deletes the one that follows them, inserted during transmission.

Two types of identifiers are defined at the link layer: Standard CAN (11 bits long) and Extended CAN (29 bits). They define the message format.

Among the higher levels, the CAL/CANopen, CAN Kingdom, DeviceNet and SDS (Smart Distributed System) specifications can be noted, more details can be found on the Internet [2].

By definition, a CAN network combines a limited number of controllers located locally within the same installation, room, or several nearby rooms. It does not go beyond the boundaries of the technological object. The ideology of the network is built on several points. First, the transmitting controller continuously listens to its own signals transmitted over the network. This makes it possible to perform bit-by-bit verification of the correctness of the transmitted information (check bit monitoring) by several nodes, in contrast, for example, to Ethernet networks. If the bit received by the controller differs from the bit transmitted by the controller, then the transmission stops and a Bit Error is generated.

When transmitting a message identifier, this mechanism is used to resolve collisions, and when transmitting information, its correctness is checked. If an error is detected in it, then the transmitter interrupts its message and issues an Error Frame on the bus to notify other nodes in the network about this event. To acknowledge receipt of a message, the data frame contains an ACK field. In this field, each node that has received the transmitted message acknowledges to its source that it has been received. An unacknowledged message is resent by the transmitter until an acknowledgment is received.

All network nodes receive transmitted information, so it is impossible to send a message to any particular node. But if modern controllers have traffic filtering tools, this is not a big problem.

The CAN network is decentralized. This can be considered a big plus, if we slightly deviate from the usual ideology, according to which the network must have a master node that controls it and slave nodes that execute its commands. In a decentralized network, nodes are more intelligent. It continues to function if any of them fail.

Information is transmitted by standard format messages - Data Frame (information transmission), Remote Transmission Request Frame or simply Remote Frame (information request), Error Frame (error message), Overload Frame (controller overload message).

The most commonly used data frames. Their format and contents are shown in Table. 1 for standard, and in table. 2 for extended frames. The information request frame differs from the informational (standard or extended format) frame only in that the RTR bit is always recessive and there is no information field.

Table 1

Field Length, bit (byte) Value
Frame start 1 Should be dominant (0)
Identifier 11
Transfer Request (RTR) 1 Should be dominant (0)
Identifier extension feature (IDE) 1 Should be dominant (0)
Reserved (rO) 1
Information field length (DLC) 4 Specified in bytes
Information field (0 - 8) Information transmitted
Checksum (CRC) 15 Calculated over the entire frame
Checksum delimiter 1 Must be recessive (1)
Confirmation interval (ACK) 1 Transmitter sends recessive (1), receiver inserts dominant (0)
Acknowledgment delimiter 1 Must be recessive (1)
End of Frame (EOF) 7 Must be recessive (1)

Table 2

Field Length, bit (byte) Value
Frame start 1 Should be dominant (0)
ID A 11 First part of identifier
Transfer Request Spoofing (SRR) 1 Must be recessive (1)
Identifier extension feature (IDE) 1 Must be recessive (1)
ID B 18 The second part of the identifier
Request to Transfer (RTR) 1 Should be dominant (0)
Reserved (r1 and r0) 2
Information field length (DLC) 4 Specified in bytes
Information field (0 - 8) Information transmitted
Checksum (CPS) of the entire frame 15 Calculated over the entire frame
Checksum delimiter 1 Must be recessive (1)
Confirmation (ACK) 1 The transmitter sends a recessive, the receiver inserts a dominant
Acknowledgment delimiter 1 Must be recessive (1)
End of Frame (EOF) 7 Must be recessive (1)

An Error Frame consists of an Error Flag field, which contains six bits of the same value (and thus violates the bitstaffing rule), and an Error Delimiter field of eight recessive bits. Its transmission causes all network nodes to register a format error and automatically transmit their Error Frames to the network. The result of this process is the automatic retransmission of information to the network by the node that transmitted the original message.

The Overload Frame repeats the structure and logic of the Error Frame, but is transmitted by a node that is currently unable to process the incoming message and therefore requests a retransmission. Currently, it is practically not used.

Each network node has a bus driver, a CAN controller (which is responsible for interacting with the network, implementing the exchange protocol) and a microcontroller. Very often, a CAN controller is combined with a microcontroller. In this case, two microcircuits are enough to create a CAN network node - a microcontroller and a bus driver.

Synchronization in CAN is closely related to the very way information is transmitted over the network. The user is given the opportunity to program the information transfer rate (from 1 Kbps to 1 Mbps), the position of the bit sampling point (moment) in its transmission interval, and the number of samples of each bit. Thanks to this, the network can be optimized for a specific application. But it also creates some problems.

Any information transmitted over the serial bus can be divided into elementary bits, the transmission time of this elementary bit NBT (Nominal Bit Time) determines the information transfer rate NBR (Nominal Bit Rate) - the number of bits transmitted per second by an ideal transmitter without restoring clock intervals:

NBR=1/NBT(1)

As shown in fig. 1, the NBT interval is divided into several non-overlapping segments, each of which consists of an integer number of time segments, called time quanta (TQ).


Fig. 1

Since the NBR transmission rate for all network nodes must be the same, using formula (1) they usually find the required NBT value and then select the duration of each of the segments forming it:

NBT=TSyncSeg + TPropSeg + TPS1 + TPS2(2)

where TSyncSeg - duration of the synchronization segment; TPropSeg - duration of the propagation segment; TPS1 - duration of phase 1 segment; TPS2 - duration of phase 2 segment.

Timing segment (SyncSeg) - first in order, used to synchronize nodes on the bus. The arrival of the initial level difference will be expected within this segment. Its duration is fixed and always equal to 1TQ.

Distribution segment (PropSeg) serves to compensate for physical signal delays between nodes. Its duration depends on the propagation time of the signal from the transmitting node to the receiving node and back, including the delays associated with the bus driver. It can take values ​​from 1TQ to 8TQ.

Phase segments 1 and 2 (PS1 and PS2) are used to compensate for phase distortion of bus drops. During clock recovery synchronization, the receiver may either lengthen PS1 or shorten PS2. According to the original specification from Bosch, the duration of PS1 and PS2 can range from 1TQ to 8TQ, but for some CAN modules, these values ​​\uXNUMXb\uXNUMXbmay be different.

Between the PS1 and PS2 segments lies a moment called the bit sampling point. It reads and interprets the logic level of the signal. In some CAN controllers, there is a mode for triple reading the signal level of each bit. But even in this case, the main point is considered to be between PS1 and PS2, and the other two contribute to the correct decision about the value of the bit according to the majority criterion (two or three samples of the same level).

As mentioned above, the nominal bit transmission time consists of an integer number of time slices TQ. The duration of the quantum depends on the frequency of the module clock generator Fosc and its division factor by the BRP prescaler. Relations between TQ, Fosc and BRP are different for different types of microcontrollers. For example, for MSR2510 the formula is valid

TQ = 2 (BRP + 1)/Fosc . (3)

For STM32F and LPC23xx microcontrollers, the formula looks like this:

TQ = (BRP + 1)/Fosc . (4)

When choosing the duration of segments, it is more convenient to use time slices TQ, rather than standard time units. Here and below, we will designate the name of the segment (for example, PropSeg) and its duration in quanta. There are several requirements that must be met:

PropSeg+PS1 ≥ PS2; (5)

PropSeg+PS1 ≥ TCork; (Xnumx)

PS2 > SJW. (7)

TCork in inequality (6) - signal propagation delay in the network. Assuming that all nodes in the network have similar internal delays, then the propagation delay can be calculated using the formula

TCork = 2 (Tbus + Tcmp + Tdrv), (one)

where Tbus - round trip time of the signal in the physical environment of the bus; Tcmp - delay in the input comparator; Tdrv - delay in the output driver.

SJW (Synchronization Jump Width - the width of the synchronization jump) in inequality (7) - the duration of the synchronization transition segment, additionally introduced to adjust the duration of receiving a bit as necessary. Used to synchronize reception with transmitted messages. In addition, external interference creates situations where the nominal transmission rate planned in the network does not correspond to the actual rate. This additional segment is also used to compensate for this difference. The duration of SJW lies within 1TQ-4TQ.

The PS1 and PS2 segments, along with the SJW, are used to compensate for the node clock drift. PS1 and PS2 can be lengthened or shortened as needed. Synchronization occurs on a transition from a recessive (1) to a dominant (0) bus state and controls the amount of time between that transition and the bit sample point. A transition is synchronized if it occurs in a SyncSeg segment, otherwise there is a phase error - the time interval between the transition and the end of the SyncSeg, measured in time slices TQ.

There are two types of synchronization: hardware and re-sync. The hardware is executed only once during the first transition from recessive to dominant, ending the rest period of the bus. This edge indicates the start of the frame (SOF - Start of Frame). Hardware sync resets the sync counter, causing the edge to lie within the SyncSeg. At this point, all receivers are synchronized with the transmitter.

Reclocking with clock recovery is performed in order to maintain the initial clock that was set by the hardware. Without clock recovery, the receivers can go out of sync due to the drift of the frequency of the clock generators in the network nodes. This timing is based on Digital Phase Locked Loop (DPLL), which compares the actual position of the recessive-to-dominant transition on the bus with the position of the expected transition within the SyncSeg and adjusts the bit timing as necessary.

The phase error e is determined by the position of the edge relative to the SyncSeg segment, measured in TQ:

e = 0 - the transition is inside the SyncSeg segment;

e > 0 - the transition is before the sampling point, time slices TQ are added to PS1;

e < 0 - the transition is after the sampling point of the previous bit, time slices TQ are subtracted from PS2.

Reclocking with clock recovery cannot occur at the beginning of a frame, since the hardware clock has already been performed there.

If the absolute value of the phase error is less than or equal to SJW, the result of hardware and resynchronization is the same. If the phase error is greater than SJW, resynchronization cannot fully compensate for the phase error.

Only one synchronization is allowed between two sample points. It maintains a set interval between the edge and the sample point, allowing the signal level to stabilize and filtering out changes that are shorter than PropSeg + PS1.

Synchronization is also related to arbitration. All nodes are tightly synchronized with the one that started to transmit first. But the signal of another node, which started transmission a little later, cannot be perfectly synchronized. However, the first transmitter will not necessarily win the arbitration, so the receivers must synchronize themselves not with it, but with the one that won it. The same happens in the ACK field, where it is necessary to synchronize with the node that first began to transmit the acknowledgment bit. All this leads to a decrease in the allowable mutual drift of the frequency of the clock generators installed in the bus nodes.

There are several synchronization rules:

- only transitions from recessive to dominant state (from one to zero) are used;

- only one synchronization is allowed within a bit transmission;

- the transition is used for synchronization, provided that the logic level of the signal read at the previous sample point differs from the level set on the bus immediately after the transition;

- the transmitting node does not restore clock intervals with a positive phase error (e > 0), i.e. it does not adjust to its own message. But the receivers synchronize as usual;

- if the absolute value of the phase error is greater than the phase jump SJW, then the duration of the corresponding phase segment (PS1 or PS2) is changed to a value equal to SJW.

The above leads to the fact that the physical length of the bus is limited by the speed of information transfer through it. All nodes on a bus need to read its states within the same bit interval. As a result, it turns out that the maximum transfer rate of 1 Mbps is achievable only with a bus length of no more than 30 m.

Consider how the CAN controller is configured in specific microcontrollers.

In microcontrollers of the LPC family (for example, the LPC23xx series), CANxBTR registers are used to set the transmission speed on the CAN bus, where x is the number of the CAN controller (there may be 1 or 2, in some cases - 4). The following parameters are set here (the intervals of the numbers of the register bits occupied by them are indicated in square brackets):

BRP (CANxBTR[9:0]) - APB bus frequency prescaler value for its further use by the CAN controller. This parameter determines the duration of the time quantum TQ, which is determined by formula (4) when F is substituted into itosc=1/TAPB, where TAPB - pulse repetition period on the system bus APB of the microcontroller.

SJW (CANxBTR[15:14]) - sync jump width in TQ quantums is one more than the value specified here.

TSEG1 (CANxBTR[19:16]) and TSEG2 (CANxBTR[20:22]) - duration of segments (respectively PS1 and PS2) in TQ quanta is one more than the values ​​specified here.

SAM (CANxBTR[23]) - sets the number of readings of the value of each bit: 0 - once, 1 - three times. The latter option is used, as a rule, in low-speed networks.

When choosing these options, you must be guided by the following rules:

TPS2 ≥ 2 TQ (9)

TPS2 ≥TSJW (10)

TPS1 ≥TPS2 (11)

The STM32F series microcontrollers have a similar register and it is called CAN_BTR. It contains the following fields:

BRP (CAN_BTR[9:0]), TS1 (CAN_BTR[19:16]) and TS2 (CAN_BTR[22:20]) - coincide in purpose and location in the register with the fields BPR, TSEG1 and TSEG2 of the CANxBTR register discussed above. When calculating the value of TQ, formula (4) should be substituted Fosc=1/TPCLK, where TPCLK - pulse repetition period on the VPB bus of the microcontroller.

SJW (CAN_BTR[25:24]) - differs from the field of the CANxBTR register of the same name only in the bits occupied in the register.

LBKM (CAN_BTR[30]) - a one in this register sets the loopback mode, in which the transmitted message is received by its own receiver, but not sent to the network.

SILM (CAN_BTR[31]) - a unit in this register sets the silent mode, in which the controller receives messages coming from the network, but does not transmit anything.

Both mentioned modes are used for debugging.

For the microcontrollers under consideration, formula (2) is simplified due to the absence of SyncSeg and PropSeg segments. They are replaced by one segment with a duration of 1TQ. The formula for them looks like this:

NBT=TQ+TPS1 + TPS2 (12)

The transmission rate on the CAN bus in bits per second is calculated in the program using the formula

NBR = (F/(BRP + 1)) (1/(PS1 +PS2 +3)) (13)

where F is the frequency of the system bus APB or VPB respectively for STM32F or LPC23xx. If the SJW parameter is non-zero, the maximum

BRMax = (F/(BRP + 1)) (1/(PS1 +PS2 - SJW + 2)) (14)

and minimum

BRmin = (F/(BRP + 1)) (1/(PS1 +PS2 + SJW + 4)) (15)

baud rate values ​​on the CAN bus, in the interval between which synchronization is provided.

The CANTools program window is shown in fig. 2. The initial data for it are the type of microcontroller, the required information transfer rate and the frequency of the system bus, from which the CAN controller is clocked. Starting the calculation, you should, first of all, choose the type of microcontroller. In the program under consideration, there are only two options - LPC23xx or STM32F103. Next, set the required transmission rate on the CAN bus in kilobits per second. After that, you can set the system bus frequency in megahertz. It remains only to press the on-screen button "Calculation" and get the result.


Fig. 2

The program works as follows: the BRP value changes in a cycle from 0 to 512. The frequency of the time slices and their number contained in the NBT interval are calculated for the given system bus frequency, BRP value and transmission rate. The number of quanta must be an integer and less than 23 - the maximum value that can be written to the registers of the microcontroller. Then iterates through the TSEG2 values ​​from 2 to 7 with a corresponding decrease in the value of TSEG1. Their sum remains constant.

The screen displays the quantum repetition rate Fsc=1/TQ, through a solid line - the duration of the TQ quantum, then the value of the BRP field of the corresponding register. After that, each pair of lines describes the result of one of the calculation options.

Parameters TSEG1 and TSEG2 in the first line of the pair correspond to the fields of the same name in the CANxBTR register of the LPC23xx microcontrollers or the fields TS1, TS2 of the CAN_BTR register of the STM32F103 microcontroller. Their sum, the value of each of the fields, as well as the value of the SJW field, if it is not null, are given. The last line displays the hexadecimal value CANBTR, which should be written to the CANxBTR or CAN_BTR register (according to the microcontroller type) to implement the calculated option.

The second line of the pair displays the values ​​of the maximum and minimum information transfer rates on the CAN bus (if SJW > 0) and the position of the sample point of the bit relative to the start of its transmission as a percentage of the duration of the transmission interval.

For some BRP values, calculation results are not displayed. This means that the time slice repetition rate or the transmission rate on the CAN bus, calculated by formula (13), turned out to be expressed as a fractional number. In such cases, no calculation is made.

The CANTools program, automating the calculation process, does not give recommendations on which combinations of parameters are best used in a real application. The network developer must choose the best option from the proposed ones, based on existing knowledge and experience. For those who have just started to master CAN, the author can recommend to be guided by the following rule: the interval between the start of a bit and the point of its sampling should be in the range from 70 to 85% of the bit duration. Perhaps, in reality, you will have to practically test several options from among those proposed by the program.

The CANTools program can be downloaded from ftp://ftp.radio.ru/pub/2014/01/can.zip.

Literature

  1. OSI network model.
  2. Controller Area Network.

Author: A. Abramovich

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Petrovich2015
The circuit is good, but the diameter of the wire of the secondary winding of the transformer is questionable with such powerful transistors


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