The 8051 IP cores are up to 15 times faster. Free Technical Library News

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8051 IP cores are 15x faster

16.05.2013

Polish IP core developer DCD has released a new version of the 8051 core that runs 15 times faster than the original. The DP8051 is the fifth generation of 8051 IP cores in Digital Core Design's list of achievements. On the Dhrystone 2.1 test program, it showed a speed increase of 11,46 to 15,55 times, which was the result of using a pipelined RISC architecture with a speed of 300 MIPS.

The speed-optimized 8-bit software kernel is designed to work with both fast (usually on-chip) and slow (external) memory. A wide range of optional features and peripherals allows engineers to tailor the kernel to specific applications and/or hardware requirements. Furthermore, the kernel has been designed with particular attention to power consumption versus performance, using an advanced power management unit (PMU), as well as 2 to 15 interrupt sources, 4 interrupt levels, 2 data pointers, a USB device, an Ethernet controller, up to 4 timers/counters, 2 UARTs, 4 I/O ports, etc. Depending on the configuration, the designer can select a compare/capture module, watchdog timer, I2C bus master/slave controller, Quad SPI, floating point coprocessor, or integer coprocessor.

The result of DP8051 in Dhrystone 2.1 was 11,46 to 15,55 times faster than the original Intel 80C51 at the same frequency. To compare the speed of the kernels, the same C compiler with the same settings was used. This speed can be used for low power devices, where the core frequency can be 10 times lower than the original implementation, without performance degradation.

The DP8051, like other DCD 8051 IP cores, has built-in support for the DoCD hardware debugger, which provides the ability to debug the entire system on a chip (SoC). Unlike other on-chip debuggers, DoCD provides debugging without interfering with a running application. It also effectively saves designer time, thanks to hardware tracing called the Instructions Smart Trace buffer (IST). IST intercepts commands without interfering with their execution, and therefore intercepts the addresses of not all executable commands, but only those related to the beginning of the trace, conditional jumps and interrupts. This method not only saves time, but also reduces the size of the IST buffer and increases the trace history. The intercepted commands are read by the DoCD-debug program, parsed and presented to the user in the form of assembler code and corresponding C commands.

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