Digital volume control. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Tone, volume controls

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When building a Highf-End UMZCH, the problem arises of choosing an IC for volume controls. Such well-known ICs as TDA 1524/1526, TSA740/730, KR 174XA53/54, TEA6300/6310/6330, LM1036 have a relatively large noise figure for Hight-End UMZCH (from -57 to -90 dB).

Features of electronic volume control:
Noise figure 70 dB
THD 0,001%
Irregularity of ACH near zero
Operating frequency range 0 - 100000 Hz
Input voltage 0,5V
Output voltage 0 - 0,5 V
Input impedance 10 kOhm
Supply voltage 7 - 20 V

Parameters such as intermodulation distortion factor (IMD) and noise figure are determined mainly by the quality of the circuit installation. Special attention to this parameter. With poor installation, capacitive and inductive couplings appear, which leads to an increase in CII, uneven frequency response and "sub-excitation". The block diagram of the device is shown in fig. 1. It consists of a digital control circuit (1), identical voltage divider blocks for the left and right channels (2) and (3). The voltage divider is built on resistors (Fig. 2).

On microcircuits DD1, DD2 integrated bidirectional switches are made, which commute the desired division ratio of the input voltage. The device has seven division ratios. The resistor values ​​are not specified. The user himself chooses the desired division factor by selecting resistors. The total resistance of the resistor chain should be 9-15 kOhm. Some recommendations for choosing resistor values: R1 - should have such a resistance at which the volume level is very low (at which it is good to fall asleep), its value is about 100 Ohms with a total circuit resistance of 10 kOhm. The resistance of resistors (kΩ) can be determined by the formulas.

R1=RU₁/U

R2=RU₁/U-R1

R3=RU₁/U - R1 - R2

R4=RU₁/U - R1 - R2 - R3

R5=RU₁ - R1 - R2 - R3 - R4

R6=RU₁/U - R1 - R2 - R3 - R4 - R5

R7=RU₁/U - R1 - R2 - R3 - R4 - R5 - R6

R8=RU₁ - R1 - R2 - R3 - R4 - R5 - R6 - R7

R9=RU₁/U - R1 - R2 - R3 - R4 - R5 - R6 - R7 - R8,

where: R is the impedance of the divider (kΩ); U - input voltage (mV), U₁ - the voltage to be obtained at the output (mV).

(click to enlarge)

Resistors are calculated in sequence from R1 to R9. The division factor is determined by the formula:

K \uXNUMXd U / U₁ = R/Rc,

where U, U₁ - input and output voltage (mV), R, Rц - total resistance and chains (counting from R1 to the desired resistor).

A schematic diagram of a digital control unit is shown in Figure 3. It includes a control unit on a DD1 chip, a reversible pulse counter DD2, a decoder DD3 that determines the desired volume level, and a voltage regulator DA1. The choice of a fixed volume level is made with the SB1 and SB2 buttons. The bounce of their contacts is eliminated by the elements DD1.1 and DD1.2. When you press the button SB1 ("+") at the output of the element DD1.1 is set to a low logic level. This level is input to the element DD1.3, at the output of which a high logic level appears, switching the counter on the DD2 chip. Since at the input of the control direction of the account (output 10 MS DD2) a high logic level from the output of the element DD1.2, the counter is increased by one.

When the SB1 button is pressed for the eighth time, the counter counts up to eight, and a log appears at pin 9 of DD3. "one". The capacitor C1 begins to charge through the resistor R5, forming a high-level pulse - the counter is reset, and the process is repeated.

When SB2 ("-") is pressed, a low logic level appears at the input of the DD1.2 element, the signal of which puts the reversible counter DD2 into subtraction mode. Since the input 15 of the counter DD2 from the output of the element DD1.3 receives a high level signal, the counter is triggered, and its readings are reduced by one. Capacitor C2 provides a delay in the receipt of the counting pulse at the output 15 of the DD2 chip when the counter switches from the summation mode to the subtraction mode and vice versa. The conditional number of the volume level (from 0 to 9) in the form of a four-bit binary code comes from the counter DD2 to the decoder DD3. The DD3 decoder converts a four-bit binary code into a positional one, while a high voltage signal appears on one of its outputs, and a low voltage signal appears on the others. The signals on the DL bus are fed to the voltage dividers of the left and right channels.

The active level is the log. "one". When the supply voltage is connected, the charge current of the capacitor C1, flowing through the resistor R4, creates a high-level pulse on it. As a result, the microcircuit is set to the initial (zero) state, in which the output of the decoder (DD5) log. "3", which, via the DL bus, enters the voltage divider unit at the control input of the bidirectional integral switch DD1 (Fig. 2.4), which connects the connection point of the resistors R2 and R1 to the output of the device. This is how management is organized.

The following electronic components can be used in the device: MLT-0,125 resistors; capacitors C1 - C8, C10, C11 (Fig. 3), C1, C2 (Fig. 2) - ceramic K10-17 or similar; electrolytic capacitor C9 - SAMSUNG. Chips can be replaced with similar series K176, K564, KR1561 or imported. Integral stabilizer (DA1) - any with a stabilization voltage of 5 V. The device is mounted on a double-sided foil board made of fiberglass.

The foil on the part side is used as a screen. The leads of the elements should be as short as possible. The signal wires leading to the device are shielded. Blocking capacitors are distributed as follows: C6 to DD1, C7 to DD2; C8 to DD3,C9,C10,C11 to DA1 (Fig. 3); C1 to DD1, C2 to DD2 (Figure 2) and soldered directly to the power pins of these microcircuits. The SB1 and SB2 buttons are displayed on the front panel of the UMZCH. The device is powered by the UMZCH power supply. Above blocks 2 and 3 (Fig. 1) there must be a screen made of thin foil.

The installation must be well thought out, otherwise the regulator will operate UNSTABLE. The device does not require adjustments, with the exception of voltage dividers (if necessary). If it is mounted without errors, it starts working immediately after the supply voltage is applied. The control of the operation of the digital part consists in checking the count of the formation of pulses coming from SB1 and SB2 in the summation and subtraction mode. Then the device is connected to the UMZCH and the possibility of adjusting the volume is checked.

Publication: cxem.net

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