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Integrated circuit INF8577CN. Reference data

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Encyclopedia of radio electronics and electrical engineering / Application of microcircuits

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The INF8577CN chip is a liquid crystal display (LCD) control device with I2With display information receiving interface. Integrated circuit INF8577CN. Reference data. The appearance of the microcircuit
The microcircuit is placed in a 40-pin DIP package (Fig. 1). Functions performed by the scheme: Rice. 1 Appearance of the microcircuit
  • LCD control in direct or duplex mode, the microcircuit controls 32 LCD segments in direct mode and 64 segments in duplex mode;
  • provision of bus interface I2WITH;
  • Can be used as bus output expander I2C.

Its features:

  • supply voltage - from 2,5 to 6 V;
  • low power consumption;
  • built-in generator for generation of LCD control signals;
  • auto-incrementing data entry;
  • the ability to switch display memory banks in direct control mode;
  • the possibility of cascading chips to increase the number of controlled segments up to 256;
  • blanking the display on power reset.

Its pinout is shown in Fig. 2, and the block diagram - in fig. 3. In fig. 4 shows the organization of the internal memory of the IP. The displayed information is stored in eight one-byte registers (their numbers are 0...7). Another similar register (control) stores the configuration information that controls the operation of the microcircuit. Registers O,2,4,6 are combined into bank "A", registers 1, 3, 5, 7 - into bank "B".

Integrated circuit INF8577CN. Reference data. Circuit pinout
Rice. 2. Pinout of the microcircuit

Integrated circuit INF8577CN. Reference data. Structural diagram of the microcircuit
Rice. 3. Structural diagram of the microcircuit

Integrated circuit INF8577CN. Reference data. Organization of the internal memory of the microcircuit
Rice. 4. Organization of the internal memory of the microcircuit

Integrated circuit INF8577CN. Reference data. Transfer of the first byte of information
Rice. 5. Transfer of the first byte of information

Bus function I2C is described in sufficient detail in [1]. Consider the features of loading information into the INF8577CN chip. The first byte (Fig. 5) transmits the address of the slave ("Slave") device. The upper 7 bits of this byte determine the device address ("Slave" address), and the eighth bit determines the direction of data transfer. If the eighth bit is zero, then data is being transmitted to the slave device, if equal to one, then this device will be the transmitter. K I2Several devices with the same "Slave" address can be connected to the C-Bus. INF8577CN can only perform the function of a receiver, so the eighth bit is always "0". Its binary "Slave" address is 0111010. Thus, the first byte always contains the code 01110100.

Table 1

Terminal designation Pin assignment Description
S1...S32 Outputs LCD segment control outputs
VR1 Enter exit When cascading for the first microcircuit - the row control output, for the remaining microcircuits - the input
A2/VR2 Enter exit The output destination is programmable. Or is it input A1. or a conclusion similar to VR1
VDD Food Positive Power Lead
A1 Sign In Address entry. The pins AO, A1, A2 are supplied with the address of the microcircuit when they are cascaded. The microcircuit will accept the data if the subaddress in the data packet matches this address.
A0/OSC Sign In The purpose of the output is determined by its connection. When connected to an RC chain, this is the input of the generator, otherwise it is the input of the address
VSS Food Negative Power Pin
SCL Sign In Clock input for I2C-tires
SDA Enter exit Data input/output for I2C-tires

Table 2

Parameter name, unit of measure designation Maximum allowable mode Limit mode
least no more least no more
Supply voltage VDD 2,5 6,0 -0,5 8,0
Input voltage, V V1 0 VDD -0,5 VDD + 0,5
Constant component of the LCD driver, mV VBP -20 20 - -
Consumption current, mA IDDISS - 0,125 -50 +50
Input current, mA I1 - - -20 +20
Output current, mA Io - - -25 +25
Reset formation voltage at power-up, V VPOR - 2 - -
Low-level input voltage at the AO output, V VIL1 0 0,05 - -
High-level input voltage at the AO output, V VIH1 VDD-0,05 VDD - -
Low-level input voltage at pin A1, V VIL2 0 0,3-VDD - -
High-level input voltage at pin A1, V VIH2 0,7-VDD VDD - -
Low-level input voltage at pin A2, V VIL3 0 0,1 - -
High level input voltage at pin A2, B VIH3 VDD-0,10 VDD - -
Low level input voltage at SCL, SDA pins, V VIL4 0 0,3-VDD - -
High-level input voltage at the SCL, SDA pins, V VIH4 0,7-VDD 6 - -
Clock signal frequency, kHz fSCL - 100 - -
Interference pulse width at I2C bus at Tenvironment = 25°С, ns tSW - 100 - -

Table 3

Parameter name, unit of measure designation Normal value Measurement mode
least no more
Consumption current, μA (V1=VDD or V1=VSS) IDD - 125 fSCL=100kHz, RCSO\u1d XNUMXMOhm, CCSO= 680 pF
75 fSCL=0kHz, RCSO\u1d XNUMXMOhm, CCSO= 680 pF
20 fSCL=0kHz, direct control mode. AO/OSC=VDD, VDD=5 V, Tenvironment= 25 °С
40 fSCL=0kHz, RCSO\u1d XNUMXMOhm, CCSO=680 pF, VDD=5 V, Tenvironment= 25 °С
Low-level output voltage at the SDA pin, V VOL - 0,4 VDD=5 V, IOL=3,0 mA
Input leakage current on terminals A1, SCL, SDA, μA IL1 -1 +1 V1=VDD or VSS
Input leakage current on terminals A2/VR2, VR1, μA IL2 -5 +5 V1=VDD or VSS
The inflowing current at the output A2 / BP2, μA IPD -5 - V1=VDD
Input leakage current at A0/OSC pin, μA IL3 -1 +1 V1=VDD
Initial generator current, µA ICSO - 5 V1=VSS
Low-level output voltage at segment control outputs, V VOL1 - 0,8 VDD=5 V, IOL1=0,3 mA
High-level output voltage at segment control outputs, V VOH1 VDD-0,8 - VDD=5 V, IOH1=0,3 mA
Output current at LCD row control pins (VR1, VR2), μA Iload 100 - VDD =5 BV0=Vss, VDD or (VSS + VDD) / 2
High-level output voltage at segment control pins, V V0:2 pm 4,5 - VDD=5 V, IOH2=100 uA
Low-level output voltage at segment control pins, V V0L2 steel construction - 0,5 VDD=5 V, IOL2=100 uA
Low-level output voltage at the segment control pins in the "off" state, V V0L3 steel construction - 0,5 VDD=2,5 V, IOL3=100 uA
Signal frequency at LCD control outputs, Hz fLCD 65 120 CCSO=680 pF, RCSO=1 MΩ

The second protocol byte I2The C-bus for the INF8577CN chip is always a control byte loaded into the corresponding register (Fig. 4). The most significant bit of this byte determines the mode of operation:

0 - LCD direct control mode (single-line mode);
1 - LCD multiplex control mode (two-line mode).

The next bit of this byte determines the LCD bank, the contents of which will be displayed on the segments in direct control mode: "0" - bank A, "1" - bank B. For multiplex control mode, this bit does not matter. The remaining six bits of this byte make up the segment vector. In fact, this vector is the address of the RAM (scheme number + register number), starting from which the loading of the displayed information begins. The segment vector combines RAM from several INF8577CN chips into a single address space. K I2Up to eight INF8577CN chips can be connected to the C-bus. The least significant three bits of the segment vector address one of the eight circuit registers, and the three most significant bits of the segment vector determine which of the INF8577CN chips will be selected. The data will be written to the chip for which these three bits match the subaddress set on the chip pins AO, A1, A2. This subaddress is formed according to the following rule:

- output A1 is an input, and it is necessary to apply an input level of zero or one to it;
- pins AO and A2 are inputs-outputs, and it is possible (but not necessary) to apply an input level of zero or one to them, or not to apply input voltage at all. In this case, the microcircuit perceives the state of the AO and A2 pins as a logical zero.

After the second byte, data transfer begins. The first byte of data is written to the RAM of one of the INF8577CN microcircuits - exactly to that microcircuit and to the place of the RAM pointed to by the segment vector. The chip that received the information generates an A-condition confirming the reception. After that, the segment vector is automatically incremented and the chips are ready to receive the next byte of data. The length of the data chain is not limited. All microcircuits track the change in the segment vector, and the data is automatically written to the RAM of the desired microcircuit. If the segment vector has reached the maximum value of 111111, then the next value will be 000000.

The increment value is 1 or 2 and is determined by the mode in which the microcircuits operate. The increment is 1 in the multiplex control mode, that is, the chip registers are loaded in a row, one after the other, regardless of which bank they belong to. In direct control mode, the increment value is 2, which ensures that either bank "A" or bank "B" is loaded, regardless of which one is displayed.

Integrated circuit INF8577CN. Reference data. Direct Controlled LCD Driver Schematic
Rice. 6. LCD driver circuit with direct control

Integrated circuit INF8577CN. Reference data. Duplex driver circuit
Rice. 7. Driver circuit with duplex control

In table. 1 shows the purpose of the IC pins, in table. 2 gives the limit and maximum allowable values ​​of the parameters, in table. 3 - basic electrical parameters. On fig. 6 shows a diagram of a direct control LCD driver, in fig. 7 is a diagram of a driver with duplex control, in fig. 8 - diagram of a 32-bit expander I2C-tires. It should be noted that in duplex control mode, it is necessary to use an LCD with two separate common terminals or two separate LCDs.

Integrated circuit INF8577CN. Reference data. 32-bit I 2 C-bus expander circuit
Rice. 8. Diagram of 32-bit expander I2C-tires

Literature

  1. K. Konov. Interface I2C on TV. - Radio amateur, 2000, N9, S.24 ... 26

Publication: cxem.net

See other articles Section Application of microcircuits.

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