ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Frequency divider by 5000. Encyclopedia of radio electronics and electrical engineering Encyclopedia of radio electronics and electrical engineering / Civil radio communications The use of a digital scale in the transceiver allows not only to improve the comfort of the operator when reading the frequency, but also in a simple way to significantly increase the stability of the GPA frequency using the CAFC system. The composition of the digital scale includes, as a rule, a quartz oscillator and a frequency divider, necessary to obtain accurate time intervals during which the pulses are counted. In principle, this generator can be excluded from the digital scale and simplified by taking advantage of the fact that the transceiver has its own quartz local oscillator. In this case, all pulse signals are automatically synchronized, since a common generator is used. In addition, the fewer generators in the device, the fewer harmonics and affected frequencies, and the design is simpler - there is an economy of radio components. Many transceivers (such as the UW3DI) use a 500 kHz local oscillator. If its signal is applied to a digital scale, having previously divided its frequency by 5000, then we will receive pulses with a stable repetition rate of 100 Hz, which in most cases are needed to form a counting time interval.
A frequency divider with such a coefficient is easy to build on a K561IE16 binary counter according to the circuit shown in fig. 1. It uses significantly fewer microcircuits than common dividers with the same ratio on decade counters. On the transistor VT1, an input amplifier-pulse shaper with a frequency of 500 kHz is assembled. The DD1 microcircuit (14-bit binary counter with serial transfer) has two inputs - setting the initial state R and counting C. The latter receives pulses from the collector of the transistor VT1. Their account occurs on falling drops (changes of a high logic level to low ones). The counter flip-flops return to their original zero state when a high logic level signal is applied to the R input. The logical node AND on the elements DD2.1, DD2.2 and DD3.1 must have as many inputs as there are units in the binary representation of the division factor. In our case 500010= 10011100010002, and the inputs of the logical node must be connected to the outputs 23 (8), 27 (128), 28(256), 29 (512) and 212 (4096). Note that the exponents correspond to the ordinal number of the digit (starting from the least significant zero) in the binary representation of the division factor. In this case, the sum of the weights of the used bits is equal to 5000 - the given division factor. When the number accumulated by the counter reaches this value, the level at the output of the element DD3.1 and the input R of the counter becomes high, the counter is reset and the counting cycle starts from the beginning. Similarly, on the K561IE16 chip, you can build a frequency divider with an arbitrary division factor, up to 214-1 (16383). It should be borne in mind that its maximum operating frequency at a supply voltage of 9 V is 4 MHz (in fact, a little more). It changes in proportion to this voltage.
The K561IE16 chip has outputs from all counter triggers, with the exception of two with weights 21 (2) and 22 (4). If just such outputs are required to implement the desired division ratio, they can be organized by connecting another low-bit binary counter in parallel with the K561IE16 (DD1) counter. For example, as shown in fig. 2, one of the counters of the K561IE10 (DD4.1) chip. When working synchronously with the counter DD1, its outputs will have a weight of 20 (1), 21 (2), 22(4) and 23(8) Capacitor C2 is used to initially set the counter to its initial state when the power is turned on. Diodes VD2, VD3 and resistor R3 form an OR node, logically summing at the input R of the counter the zeroing pulses when the power is turned on and coming from the output of the DD3.1 element. It should be noted that after turning off the power, the duration of the discharge of the capacitor C2 can reach several minutes. To reduce it, if necessary, we recommend connecting a 2 MΩ resistor in parallel with capacitor C1. Author: Olga Leznaya See other articles Section Civil radio communications. Read and write useful comments on this article. Latest news of science and technology, new electronics: Machine for thinning flowers in gardens
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