Fast mains voltage comparator on a CMOS chip. Encyclopedia of radio electronics and electrical engineering

Encyclopedia of radio electronics and electrical engineering / Protection of equipment from emergency operation of the network, uninterruptible power supplies

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An important part of an uninterruptible power supply, a high-speed discrete mains voltage stabilizer or an emergency voltage deviation protection device is a mains voltage monitoring unit or a mains voltage comparator (VSC). Seeming at first glance, the simplicity of the problem is deceptive. The difficulty is that there is an alternating or pulsating voltage at the input of the KSN, and the output signal of the KSN must be continuous.

In this case, various RC and LC filters cannot be used for smoothing, since they introduce a significant delay in the response of the CSN to a change in the mains voltage. Therefore, the KSN must compare the input voltage with the reference voltage periodically, synchronously with the mains frequency, and remember the result of the previous comparison until the next one. Since the mains voltage is sinusoidal and usually has a low harmonic coefficient (<6%), it is possible to control the amplitude value of the mains voltage and use it to judge the magnitude of the effective voltage value. The so-called peak detector [3] can be used as a voltage amplitude detector. The disadvantage of using a peak detector is that it must be reset every time before a new measurement.

A more functionally simple device can be built on a restartable single vibrator with a circuit for controlling the excess of the mains voltage level. In this case, the circuit can be assembled on digital microcircuits, in particular on CMOS circuits. This choice is not accidental, since the switching parameters of CMOS circuits have exceptionally high temperature stability [1]: fluctuations in the temperature of the medium in the range from -55 to +125°C change individual sections of the transfer characteristic by no more than 5%. It should be expected that in the temperature range from +15 to +35°C (which is typical for residential premises), the transfer characteristics will change by no more than 0,6%, which is much better than the required 1...2%. In addition, CMOS circuits have exceptionally low power consumption, which can be important when using SSNs in tracking devices.

(click to enlarge)

In the circuit (Fig. 1), the investigated, pre-rectified, mains voltage is supplied to the INPUT input. If galvanic isolation is required, the mains voltage is supplied through an isolating transformer. With the help of a divider consisting of a tuning resistor R1 and resistors R2, R3, KSN is adjusted to a certain threshold. Divider resistor values ​​are specified for the case when +UP=5 V, and the voltage amplitude at the INPUT input is 17 V (~12 V rms). Capacitor C1 is used to filter short impulse noise penetrating from the network. Diode VD1 limits the output voltage of the divider at +UP. On the first three inverters DD1 and resistors R4, R5, a Schmitt trigger is assembled, which is triggered when the mains voltage reaches the trigger level Us1.

The restartable one-shot (SW) consists of a KS-chain R6, C2 and a Schmitt trigger assembled on the remaining three inverters and resistors R7, R9. Resistor R8 is required to obtain the response hysteresis of the entire device. +UP refers to the supply voltage of the 3...15 V CMOS circuit.

Figure 2 shows the timing diagrams for the SSN circuit shown in fig. 1. While the amplitude of the mains voltage has not reached the threshold Uc1 of the Schmitt trigger, its output (pin 6 DD1) has a high logic level (LU). At the output OUTPUT KSN (pin 8 DD1) there is a low LU, indicating that the mains voltage is below a predetermined level.

As soon as the amplitude of the mains voltage exceeds the threshold Uc1 of the Schmitt trigger, at its output (pin 6 DD1) low LU pulses will appear, synchronous with the mains frequency. These pulses are fed through the VD1 diode to the software input. The time constant of the R6C2 RC circuit is chosen such that the output of the software remains a continuous high level while triggering pulses from the output of the Schmitt trigger are received at its input. Therefore, the output of the OUTPUT of the KSN will be high LU, as long as the mains voltage is above the specified level.

Figure 3 shows a simplified diagram of the KSN on a smaller number of inverters. The difference between this scheme and the KSN scheme shown in Fig. 1 is that it does not traditionally include the R6C2 RC chain.

(click to enlarge)

The SPVs described above (let's call them the SPVs of the first type) are the most effective in controlling the increase in the mains voltage above a given level. When the mains voltage fails, this circuit generates a signal to lower the level of the network with a time delay of 7 ... 10 ms, due to the time constant of charging the RC circuit of the software.

Partially getting rid of the specified delay when monitoring the mains voltage drop below a predetermined level allows the SPV of the second type, which operates on the principle of measuring the pause duration DT, when the instantaneous voltage of the half-sine wave at the INPUT input is less than Uc (Fig. 4).

The amplitude Ua of the measured mains voltage determines the interval DT according to the expression

DT=arcsin(Uc/Ua)/πf.

The nonlinearity of the measured voltage curve in the time interval DT=10° can be neglected [2]. If DT=10°, then Ua=11Uc, and the delay in the operation of the KSN when the mains voltage drops is approximately 0,6 ms.

The scheme of the CSN operating according to the indicated principle is shown in Fig. 5, and the timing diagrams are shown in Fig. 6.

(click to enlarge)

Using the input divider R1, R2, R3 achieve the required ratio of Ua and Uc. Since Uc in our case is equal to the switching voltage of the CMOS circuit, which is equal to UP / 2, it is necessary to select Ua=0,6UP to obtain a delay <5,5 ms.

Diode VD1 limits the output voltage of the divider at +UP. The voltage from the output of the divider is fed to the input of the comparator, which is a Schmitt trigger, assembled on the first two DD1 inverters. The comparator is necessary for the formation of high LU pulses when the level of the half-sine wave exceeds the threshold Uc. The high LU at the output of the comparator through the diode VD2 is fed to the input of the first software, assembled on the third and fourth inverters DD1, on resistors R7, R9, R10 and capacitor C2.

The trimmer resistor R1 achieves a continuous high LU signal at the output of the software at a mains voltage higher than the specified one. When the mains voltage drops, low-LU pulses appear at the output of the first software, which are fed through the VD3 diode to the input of the second software, assembled on the fifth and sixth DDI inverters, resistors R6, R11, R12 and capacitor C3. From these pulses at the output of the OUTPUT KSN, the second software generates a continuous low LU, signaling that the mains voltage is below a predetermined level or is completely absent. Resistor R8 serves to obtain the required hysteresis of the switching characteristic of the CV. From the timing diagram (Fig. 6) it can be seen that with an increase in the mains voltage, a high LU at the output of the second type of SPV is formed with a delay of about 10 ms.

When repeating circuit solutions, it should be borne in mind that due to some variation in the switching parameters of CMOS circuits, it may be necessary to clarify the value of the resistor R6 of RC circuits. To obtain the hysteresis of the switching characteristics of the KSN, it is necessary to clarify the value of the resistor R8 in the positive feedback circuit.

References:

1. Zeldin B.A. Digital integrated circuits in information-measuring equipment. - L .: Energoatomizdat, 1986.
2. Milovzorov V.P., Musolin A.K. Discrete stabilizers and voltage shapers. - M.: Energoatomizdat, 1986.
3. Peyton A.J., Walsh V. Analog electronics on operational amplifiers. - M .: Binom, 1994.

Author: V. Ya. Volodin

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