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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING 8XC51CB microcontrollers from INTEL. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Microcontrollers The 8XC51GB group includes microcontrollers 80C51GB, 83C51GB, 87C51GB, 80C51GB-1, 83C51GB-1 and 87C51GB-1. At the time of writing, all of them were produced in a 68-pin PLCC package and were marked with the N prefix (N80C51GB, N83C51GB, etc.). The chips are made according to SNMOS III-E technology from Intel. Versions with a programmable internal ROM do not have a transparent window in the case, i.e. they belong to the category of one-time programmable ones. This somewhat limits the circle of their consumers due to the fact that during debugging it is not possible to work by trial and error with repeated reprogramming of the crystal, but it is necessary to use the appropriate emulator. The first three of the above controllers operate at a clock signal frequency of 3,5 to 12 MHz, the rest operate in the frequency range of 3,5 ... 16 MHz. The supply voltage of all controllers is 5 V, low-voltage versions were not produced. Main technical characteristics of controllers of group 8хС51GB:
Most of these characteristics are inherent in the entire MSS51 family, and therefore we will not dwell on them in detail. For those who are not familiar with them, we recommend that you refer to the articles on single-chip microcomputers published in [1-3]. In addition, when analyzing microcontrollers 8xC51Fx, 8x151Fx [4], an array of programmable counters was described in detail, and therefore it will also be considered only from the point of view of its differences from that available in 8xX51Fx. The subject of our acquaintance will be those of the features of 8xC51GB that none of the other groups of the MCS51 family have. Note that the 80C51GB and 80C51GB-1 controllers do not contain internal program memory, 83C51GB and 83C51GB-1 have a mask-programmable ROM with a capacity of 8 and 16 KB, respectively, and 87C51GB and 87C51GB-1 have a reprogrammable ROM with a capacity of 8 and 32 KB, respectively. PURPOSE OF CONCLUSIONS The purpose of the conclusions of the controllers of the group in question is as follows:
Most of these conclusions are familiar to those who have already dealt with microcontrollers of the MSS51 family. New are the pins of the P4, P5 ports with their alternative functions (they are given after the sign /), power pins (AVrol, AVss) and signals associated with the ADC (COMPREF, ACH0-ACH7, TRIGIN), which will be considered when describing the corresponding devices. The RO port is similar to the corresponding ports of earlier microcircuits and performs the same functions. The 8xC51GB controllers have two new ports - P4 and P5. As well as R1-RZ. they are eight-bit quasi-bidirectional I/O ports with a high internal resistor to ensure that the outputs go to logic 1 quickly when switched. The resistor is connected to the output stage for two clock cycles to bring the output to the specified state, and then disconnected. The outputs of ports P1-P5, which are in the logic 1 state, have a high potential due to the internal resistor and can be used as inputs in this state. Unlike RO, the input lines of ports P1-P5 are equipped with Schmitt triggers. Almost all port pins have an alternative purpose (Table 1). When reset, the outputs of the RH port are set to a single state, the rest are set to zero. RESET# input - reset. A low level on this input for two machine cycles while the clock generator is running causes the controller to reset. The port pins are set to their initial state at the moment when the voltage at the RESET# input drops to 0,3...0,4 V. The reset procedure lasts five machine cycles (60 clock cycles). It is necessary to pay attention to the fact that the polarity of the reset signals of the microcontrollers of the 8xC81GB group is the opposite with respect to other microcircuits of the MSS51 family. The reasons for this inversion are unknown to the author. The ALE/PROG# input is completely similar to the corresponding input of other controllers of the MSS51 family. Note that in 8xC51GB, the user has the ability to disable the output of the ALE signal. by setting the least significant bit of the SFR register, located at address 0EH, to 8. The A1E signal is issued only at the time of the action of the MO\/C or MO\/X command, in other cases, a single level is held at this output. When working only with the internal program and data memory, there will be no signals at the ALE output at all. The EA#/Vpp input is used to enable fetching commands from the internal program memory, if there is one on the chip and the input is connected to a common wire. When a single level is applied to it, the program from the external program memory is executed. However, the latter is possible only until the protection bits of the internal program memory are set, which will be discussed below. The programming voltage Vpp = 12,75 V is applied to this pin when programming the internal ROM of the 87C51GB, 87C51GB-1 microcircuits. DIFFERENCES 8ХС51GВ FROM OTHER PRODUCTS OF THE MCS51 FAMILY So, let's list the most significant differences between the 8xC51GB controllers. It:
NODE ADC The ADC of microcontrollers 8хС51GB (see the functional diagram in Fig. 1) has eight analog inputs (outputs ASN0-ACN7), an external trigger input TRIGIN, power supply (AVHrol) and common wire (AVss) outputs of the analog part, galvanically isolated from the corresponding digital outputs, as well as the output of the reference (exemplary) comparison voltage COMPREF. The ADC includes an eight-channel multiplexer, a 256-element resistive array, a comparator, a sample/hold device, eight result registers, a successive approximation register, and a comparison result register. In fact, there are 10 additional registers in the SFR space. Registers AD0-AD7 (84Н, 94Н, 0А4Н, 0В4Н, 0С4Н, 0D4Н, 0Е4Н, 0F4Н) contain the conversion results for each of the eight channels. The value of each register is updated upon completion of the conversion in the corresponding channel, starting from channel 0. The comparison results register ACMP (0С7Н) contains eight flags that reflect the results of comparing the signals at the analog inputs ASN0-ACN7 with the voltage at the COMPREF input (Table 3). The corresponding flag is set to 1 if the input voltage at this analog input exceeds COMPREF" otherwise the flag is cleared. The ACOM register (097H) contains the ADC interrupt flag ALF, the ACE conversion enable bit, two channel selection bits ACSO and ACS1, AIM input mode and ATM startup mode bits (Table 4).
COMPARE MODE This mode is always active and is used to compare the voltages at the ACH0-ACN7 inputs with the reference voltage supplied to the controller's COMPREF input. Each time the ADC is started, the state of each bit of the ASMR register changes to a new one, starting from channel 0, regardless of the set channel polling mode. The mode allows you to quickly compare the type of more or less two analog signals using a hardware method, which can significantly reduce and simplify the program being executed. If compare mode is not used, any voltage from Vcc to Vss can be applied to the COMPREF input. START MODE The ADC can be triggered from both internal and external sources. In the first case, the ATM bit of the ACON register must be set to 1. In this mode, in the cycle following the one in which the ACE bit was set to 1, the conversion starts from channel 0. After the conversion is completed, the ALF flag is set on the seventh channel. ADC enabled, setting the flag to 1 causes an interrupt on the ADC vector. A new cycle begins after the completion of the previous one. Setting the ACE bit to 0 ends the conversion, In external trigger mode, the conversion starts when there is a zero level at the TRIGIN input. This input is not edge latching and its state is determined by polling every machine cycle. In other words, to start the conversion, the duration of the zero-level signal at the TRIGIN input must be greater than the duration of the machine cycle. After the loop starts until it completes, the status of the TRIGIN input is ignored and the conversion is carried out in the same way as in the previous case. After the cycle is completed, the ADC stops until a new pulse arrives at the TRIGIN input or until it is internally triggered by the ACE bit.
LOGIN MODE Setting the AIM bit to 0 puts the ADC into the so-called scan mode, in which the conversion is carried out in the sequence ACH1, ACH7 ..... ACH1. The results of the conversion are placed respectively in the ADO registers. AD7.....ADXNUMX. When the AIM bit is set to 1 after the start of the ADC, four consecutive signal conversions are performed in the channel, the number of which is determined by the state of the ACS0 and ACS1 bits of the ACON register. The results of these signal measurements on the selected channel are written to registers AD0-AD3. After that ADC. as in scan mode, polls channels ACH4-ACN7. the conversion results are recorded in AD4-AD7. USING ADC FOR LESS CHANNELS
There are several options for using ADCs with less than eight channels. If the conversion time is not critical, then you can simply wait for the interrupt after the completion of the conversion in the seventh channel and read the results only from the selected channels. If it is important to get the result immediately after the conversion is completed in the selected channel, Intel suggests counting the desired time interval using a timer and its interrupts. Another recommended method is to periodically poll the status of the corresponding result register. Its change gives information that a new conversion has taken place (however, this method is only suitable if the measured voltage is not constant). Using the channel selection mode does not reduce the conversion time, but only increases the number of measurements in the selected channel per cycle. ADC IN MICROPOWER MODE The ADC of the 8xC51GB controllers includes a circuit that limits the power consumption of the node in XX and MP modes to the value of the leakage current. For the normal functioning of this circuit, the potential of Use must be applied to the AVioi pin of the microcontroller. During the time the ADC is in low power mode, the supply voltage can be reduced to 2,5 V. ARRAYS OF PROGRAMMABLE COUNTERS The 8xC51GB microcontroller includes a programmable counter array (PCA), similar to that used in 8xC51Fx [4]. However, 8xC51GB also has a second similar array - PCA1. Its differences from RSA are as follows:
Microcontrollers 8хС51GB support 15 interrupt vectors (tab. 6). The lower five of them are similar to those available in all controllers of the MSS51 family, the sixth serves the third timer / counter (it appeared only starting with the crystals of the MSS52 family), the seventh, available only in 8xC51FX, 8x151FX and 8xC51GB, supports a programmable counter matrix (PCA). The latter additionally has interrupts from five external inputs (INT2 - INT6). second matrix of programmable counters, ADC and extended serial port.
In all controllers of the MSS51 family, each interrupt can be disabled by setting the corresponding bit in the IE register to a low level. Naturally, this is also true for 8xC51GB. However, since it contains twice as many interrupt sources, an additional IEA register is used to enable/disable them (Table 7). As in the previous case, setting the bit to 1 enables the corresponding interrupt, reset to 0 disables it. Register address IEA-0A7H. Note that all interrupts, including those described in Table. 7 can be simultaneously disabled by setting bit EA (IE.0), the most significant bit of register IE, to 7.
Each interrupt can have its own priority (from level 0 - the lowest, to level 3 - the highest). The priority level is determined by the state of the bits in the IP, IPH and IPA, IPHA register pairs. The first of these is identical to those found in earlier controllers and is described in detail when considering group 8xC51Fx. The second pair (register addresses 0V8H and 0V6H, respectively) is available only in 8xC51GB and serves interrupts that are only in these controllers. In table. 8 shows the correspondence between the bits of the registers and the interrupts, the level of which they determine, in table. 9 - correspondence between the priority levels and the state of the bits in the register pairs IP, IPH and IPA, IPHA.
Low priority interrupts can in turn only be interrupted by an event of higher (but not equal) priority. Accordingly, an interrupt with the highest priority cannot be interrupted. If the processor simultaneously receives requests for two or more interrupts with the same priority, then the order in which they are processed is determined by a special interrupt flag polling sequence. For 8xС51GB controllers, it looks like this:
External interrupts I NT0 and INT1 of the 8xC51GB microcontroller fully correspond to similar interrupts of all microcircuits of the MSS51 family and, depending on the state of the ITO and IT1 bits of the TCON register, can be fixed both in level and in difference from 1 to 0. External pins INT2 and INTZ can respond to both positive and negative edge of the signal. The microcircuit has an EXICON register (0С6Н) containing bits IT2 and ITZ, which determine the active edge of the signal at the pins P5.2 (INT2) and P5.3 (INTТЗ). When the ITn bit is set to 0, the interrupt is initiated on a negative edge, when ITn = 1, on a positive edge. External events INT4 - INT6 are fixed only on a positive edge at the outputs P5.4(INT4) - P5.6(INT6). All external interrupts generate corresponding hardware-settable flags. For INTO events, INT1 are bits 1E0 and IE1 of the TCON register. The IE2-IE6 flags are in the EXICON register. They are reset by hardware at the moment the processor switches to the corresponding interrupt processing routine. During the machine cycle, external interrupt pins are polled only once. Therefore, in order for an interrupt to be registered, the duration of its active level must exceed the duration of one machine cycle (12 clock cycles). The purpose of the EXICON register bits is given in Table. 10.
ADVANCED SERIAL PORT The Enhanced Serial Port (SEP) has the hardware to implement the 1C-bus, the de facto standard for serial communications. SEP allows operation in four different modes, has three different clock sources. For his needs, two outputs of the microcircuit are involved: P4.1 - data input / output and P4.0 - to output the clock signal. A transmitted or received packet consists of eight data bits. In this case, eight cycles of SEP operation are used. In the absence of received or transmitted information, the clock signal and data are inactive. Three SFR registers are assigned to SEP: SEPCON (0D7H), SEPDAT (0E7H) and SEPSTAT (0F7H). They are only addressed byte by byte. The assignment of bits in the SEPCON and SEPSTAT registers is given in Table. 11 and 12, respectively.
On fig. Figure 2 shows the distinguishing features of the SEP operating modes - the active levels of the clock signal and the edges used for receiving or transmitting. As follows from Table. 11, the SEP mode of operation is determined by the state of the CLKPOL and CLKPH bits located in the SEPCON register.
To receive or transmit a byte, the user must select the port operation mode (CLKPOL and CLKPH bits), the baud rate (SEPS1 and SEPS0) and set the SEPE bit to 1. The transfer process begins immediately after the byte is loaded into the SEPDATA register. A receive is initiated by setting the SEPREN bit to 1 when the SEPDATA register is empty and there is no transmission. After receiving eight bits, SEPREN is reset by hardware. The completion of a receive or transmit causes the SEPIF bit to be set to 1. Its reset is possible only by software. If the user attempts to write to (or read from) the SEPDATA register while transmitting or receiving, the corresponding error bit is set. The SEPFWR flag is set when attempting to do so during a byte transmission, and SEPFRD is set during a receive. There are no interrupts associated with setting these bits, so the user must control their state independently. Naturally, resetting these flags can only be done programmatically. HARDWARE TIMER The hardware watchdog timer (HWDT) resets the microcontroller when it overflows, which is a means of combating a system hang (program loop). The timer/counter of PCA module 4 can also be configured to perform a similar function, but such use limits the user's capabilities, and therefore an independent WDT appeared in 8xC51GB that does not require the use of PCA. The hardware watchdog consists of a 14-bit counter that is incremented every machine cycle and the SFR register WDTRST (0A6H). The timer is always active and continuously increments the counter while the clock is running. There is no means to stop the timer. If the user program does not write any information to WDTRST, then every 16 machine cycles, the HWDT generates a RESET signal, which resets the microcontroller. This resets the counter. To prevent the operation of the HWDT, the user program with an interval of at least 384 machine cyclones must sequentially enter two bytes into the WDTRST register - 16EH and 383A01H. Note that in WDTRST you can only write information, there are no means of reading its contents. It is not recommended to perform the said restart of the watchdog timer using an interrupt service routine from one of the timers / counters, since interrupts can be processed even when the main program is hung. The best place to place watchdog reset commands is in a looping piece of code that has a repeat period less than the HWDT's firing time.
Putting the 8xC51GB into micro-power mode stops the internal clock and HWDT. The removal of the controller from the micro-power mode, like all its predecessors, can be done in two ways: by resetting or by calling an external interrupt, enabled before the 8xC51GB is switched to the named mode. In the first case, the HWDT is reset, in the second, at the start of the clock generator, the contents of the HWDT counter will continue to increase. But since for a stable start of the clock generator, a time of about two dozen of its periods is required, it is recommended that the duration of the external interrupt pulse, which brings the controller out of the micro-consumption mode, be no less than the mentioned time. The interrupt handler will start executing only after the external interrupt signal level goes to 1, when the generation frequency stabilizes. At the same time, the incrementing of the HWDT counter will begin, that is, while the interrupt signal has a zero level, the HWDT does not work. In XX mode, the controller clock generator is not disabled. As a result, the content of the HWDT counter is continuously increasing, and to prevent a reset, it is necessary to use a timer interrupt, which will exit this mode, reset the watchdog timer counter, and return to the Idle mode. The following code snippet uses the T/CO interrupt to periodically reset the HWDT. True, as noted above, using such an interrupt is not the best place to reset the counter, and it is better to build such a procedure into a periodically executed part of the program - polling the keyboard or displaying information. Therefore, the above fragment should be considered as a demonstration example, and not as a subroutine that should be used in programs without any changes. CLOCK FAILURE DETECTION The Oscillator Failure Detection (OFD) circuit is designed to reset the microcontroller if the oscillator frequency falls below a specification limit. If after the reset the clock frequency does not change (or rather, does not increase to an acceptable value), the controller will remain in this state. Note that exceeding the frequency above the set limit does not lead to its reset. The OFD circuit always turns on after a reset or when the controller exits the micro-demand mode. To disable it, write 0E1H and 01EH in sequence to the OSCR register (0A5H). This must be done, in particular, before switching to the micro-consumption mode, since the clock generator is turned off in it. The circuit can be allowed to work again only by resetting or exiting the micro-consumption mode by an external interrupt. The state of the OFD circuit can be determined by reading the OSCR register. If OSCR=0FFH, fault detection is enabled, if OSCR=0FEH, it is disabled, CONCLUSION So, we have finished reviewing the features of eight-bit microcontrollers of the MCS51 family, developed and manufactured by Intel. They turned out to be so successful that the replication of many of them (with some technological improvements) continues to this day. Steady demand for these controllers is determined by the fact that hundreds of thousands of developers have become accustomed to them, have developed a huge amount of software, and have acquired a fleet of debugging and cross-tools. In many cases, a new development does not require replacing the microcontroller with something radically new, and therefore it is more expedient to carry it out on what is already familiar and provided with support tools, rather than spending effort and money on switching to a different element base. For this reason, Intel has regularly improved its controllers to expand the range of tasks solved with their use. Moreover, firms that had no relation to the original development joined this improvement. So, today, microcontrollers compatible with this family are produced by Philips, Siemens, Dallas Semiconductor, Atmel, OKI and some less well-known manufacturers, including a number of enterprises in the former USSR. All controllers have the same set of commands and basic architecture, as a rule, are compatible in "pinout" and have similar programming algorithms. However, there are significant differences in the set of additional registers and hardware. So, microcontrollers from Dallas Semiconductor have two DPTR registers and a mechanism for switching them, Philips products have an ADC of increased capacity, Siemens controllers often have external memory on the chip, addressed by MOVX commands, etc. Literature
Author: A.Frunze, Moscow
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