ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Frequency dividers with a fractional division factor. Encyclopedia of radio electronics and electrical engineering Encyclopedia of radio electronics and electrical engineering / Radio amateur designer In some cases, to obtain the required frequency using the existing quartz resonator, a divider with a non-integer (multiple of 0,5) division factor is required. The author tells about one of the variants of such a divider and about the practical design with its use. The literature describes a method for reducing the division factor of the counter by one using the "XOR" element. It turned out that this method can also be used to obtain a fractional division coefficient. As an example, consider the circuit in Fig. 1. The division ratio of the counter DD2 output 4 is equal to eight. If an element DD1.1 is connected to its input, each change in the signal at the output of the counter will invert the signal at the input of the CP of the DD2 chip (Fig. 2) and, as a result, an earlier (by 1/2 period of the input signal) next change in the state of the counter . As a result, the pulse frequency at output 4 of the DD2 chip will be seven times less than the input, and at output 2 - 3,5 times. It is important to note here: if the duty cycle of the pulses at the output of the counter without the "XOR" element is equal to two and the "meander" signal is also fed to the input of the divider, a signal of the same shape is obtained at the output. Under these conditions, the signal at the penultimate output 2 retains its periodicity, but its duty cycle is no longer equal to two, and the signal at output 1, although it has an average frequency that is 1,75 times lower than the output, is non-periodic (more precisely, pairs of pulses are periodic in it) . Thus, to obtain a divisor with a division factor ending in 0,5, you should round the required factor upwards and double the result. As the basis of the necessary divider, take the counter with the resulting conversion factor, cover it with feedback through the XOR element and remove the output signal from the penultimate stage. Consider a practical example of using this method. To obtain a frequency of 440 Hz (electronic tuning fork) from the frequency of the resonator of an electronic clock (32 Hz), a divider with a factor of 768 is required. To obtain it, a frequency divider by 150 is used, the conversion factor of which is reduced to 149 by connecting the XOR element, and the output signal is taken from its penultimate output. The scheme of the device is shown in fig. 3. The master oscillator is assembled on the element DD1.1. It should be noted that due to the asymmetry of the inputs of the "XOR" logic elements, such a generator only works when the inputs 2, 5, 9 or 12 are connected to the power plus [1]. The frequency divider counter by 149 is assembled on DD2-DD4 microcircuits and the DD1.2 element. The division ratio of each counter DD2 and DD3 is equal to five. Their output is taken from the 2 outputs purely for PCB layout convenience; it was possible to use any outputs from 0 to 4. The frequency division of the output signal of the DD3 counter by six (150 = 5x5x6) is carried out by the DD4 chip - K176IE3. The main purpose of this microcircuit is to work in an electronic clock. For use in this device, it is interesting in that it divides the frequency by six by outputs b, c, e, f, g, 2 and p, by three by outputs a, d, and the signal is periodic at all outputs, including a and d, and at the output f its duty cycle is two. Therefore, if a signal is supplied to the lower input of the element DD1.2 from the output f ("meander"), at the output a or d a periodic signal is received with a frequency 74,5 times less than the original one. Timing diagrams in fig. 4 illustrate that the XOR control signal need not have a duty cycle of two. In the described device, the signal from output 2 of the DD4 chip is used. Its duty cycle is 1,5. Despite this, the periodicity of the pulses at the output a is preserved. This is because each change in the signal that controls element DD1.2 falls either at the beginning of the pulse at the output a, or at its middle. As a result, the duration of the pulses on this output is reduced by half the period of the input frequency, while the duration of the pauses remains unchanged (in Fig. 4, the durations of the pulses and pauses between them are shown in periods of a frequency of 32 Hz). Thus, at the output a of the DD4 microcircuit, a signal is generated with a frequency of 440 Hz and a duty cycle close to 1,5. It is fed to the inputs of the buffer elements DD1.3 and DD1.4. The first one inverts the input signal, the second repeats it. A signal is applied to the piezoelectric sound emitter, connected between the outputs of these elements, with a swing (from peak to peak) equal to twice the supply voltage, which increases the sound volume, which is regulated by resistor R4. The current consumed from the battery does not exceed 5 mA. The differentiating circuit C3R3 is designed to correctly set the triggers of the DD4 chip to its original state. The fact is that the counters of the K176IE3, K176IE4, K561IE9, K561IE8, K176IE8 microcircuits are based on cross-linked shift registers, and their triggers can be set to an arbitrary state when turned on. For the last three types of microcircuits, this does not matter, since they contain circuits for automatically correcting an incorrect initial state and, after applying several clock pulses to them, go into the allowed one [2]. The K176IE3 and K176IE4 microcircuits do not contain such circuits, therefore, without the initial setting of the triggers in the desired state, they may not work correctly. Literature
Author: S. Biryukov, Moscow See other articles Section Radio amateur designer. Read and write useful comments on this article. Latest news of science and technology, new electronics: A New Way to Control and Manipulate Optical Signals
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