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Decoupling strategies for PCB. Encyclopedia of radio electronics and electrical engineering

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Encyclopedia of radio electronics and electrical engineering / Computers

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Good decoupling methods reduce the number of decoupling capacitors.

The main thing is the correct choice of capacitors and competent wiring.

1. LOGIC SWITCHING CURRENTS

It's no secret that when changing logical states, most digital devices experience a large inrush current that immediately follows the front of the clock signal (Fig. 1).

Decoupling strategies for PCB

For example, a circuit running at 100 MHz and drawing about 4 A on average might actually require 20 A of current during the first few nanoseconds of the clock sequence. (The reason for the occurrence of large currents when changing logical states is considered in the article by B. Carter "Printed Circuit Board Layout Technique", elart.narod.ru/articles/article11/article11.htm - translator's note.)

Obviously, powering this circuit from a 20-amp source will increase the size and cost of the product. Less obviously, parasitic series inductances in lead wires, PCB traces, and component leads can make it impossible for a large power supply to respond quickly to instantaneous current changes. On the other hand, insufficient load capacity of the source will lead to unstable voltage drops on the power and ground rails. This phenomenon usually manifests itself as high frequency noise.

 

2. APPLICATION OF CAPACITORS AS POWER DEPOSIT ELEMENTS

The use of decoupling capacitors makes it possible to distribute the operating current between consumers using low-impedance (i.e., low inductance for RF currents) current paths. In practice, this means that the decoupling capacitors directly service the digital components, while the power supply takes care of recharging them. The key to creating a workable and successful decoupling circuit is the correct choice of capacitors used and the correct wiring of their connection circuits.

Using capacitors as decoupling elements requires understanding the basics of how they work. Figure 2a shows an ideal capacitor - a capacitance for accumulating and storing charge and for releasing it. Figure 3 shows the frequency dependence of the impedance of an ideal capacitor - a monotonic decrease in value with increasing frequency. Because the dominant noise in digital systems is high frequency noise (>50 MHz), the reduction in impedance at high frequencies is well suited to power decoupling.

Decoupling strategies for PCB

Unfortunately, the behavior of a real capacitor is not that simple; its model is shown in Figure 2b. The physical design of a real capacitor includes an equivalent series resistance (ESR) and an equivalent series inductance (ESL). In addition, a real capacitor has leakage resistance. The sum of these parasitic effects leads to a change in the nature of the frequency dependence of the impedance (Fig. 3).

Decoupling strategies for PCB

The lowest point of the impedance dependence is known as the self-resonant frequency. Designers often try to find capacitors with a natural resonant frequency that is close to the operating frequency of the system. However, the parameters of real capacitors make this selection impractical at clock frequencies exceeding 100 MHz. An important rule to remember: decoupling capacitors can be used at frequencies lower than their own resonance frequency, as long as their impedance at these frequencies remains low enough.

The voltage drop across the equivalent series resistance of a capacitor is proportional to the current flowing through it. Since it is important to keep the supply voltage stable, it is desirable to use capacitors with low ESR (ie, less than 200 mΩ) in decoupling circuits. The equivalent series inductance determines how quickly a capacitor responds to current changes - capacitors with a lower ESL value will respond more quickly to changes in current flow, which is very important for high frequency decoupling circuits. Although, as a parameter, ESR is more widely described and studied, ESL is probably more important. All surface mount capacitors listed in Table 1 have fairly low ESL values.

Standard size

ESL min (nH)

ESL max (nH)

0402

0,54

1,90

0603

0,54

1,95

0805

0,70

1,94

1206

1,37

2,26

1210

0,61

1,55

1812

0,91

2,25

with radial leads

6,0

15,0

with axial leads

12,0

20,0

Capacitors with type I dielectric material do not degrade their performance with time and temperature, but the low value of the dielectric constant makes their use as decoupling components inefficient. Capacitors with type II material (i.e. X7R) are the better choice due to good long term stability (10% loss over 10 years), thermal performance and high dielectric constant. Type III material has the highest dielectric constant and poor thermal performance (50 to 75% loss at extreme temperatures) and poor long-term stability (20% loss over 10 years). Among popular dielectrics, multilayer ceramics and synthetics have small equivalent series inductance and resistance. Ceramic capacitors are more easily accessible. Tantalum capacitors are often used as general low frequency decouplers, however they are not suitable for local decoupling.

Table 1 shows typical ESL values ​​for various types of capacitor packages. Size is the defining element of the equivalent series inductance - usually a smaller capacitor will have a lower ESL for the same value of capacitance. Capacitors with high ESL values ​​are not suitable for use as decoupling elements.

In general, the correct strategy is to find the capacitor with the highest capacitance in the smallest overall dimensions. However, you need to be careful with this choice. The height of the capacitor case has a significant effect on the ESL. For the overlapping ESL ranges in Table 1, a package with a smaller PCB footprint can be selected. However, the ESL value may be large. Therefore, when choosing a capacitor type, it is necessary to be guided by the manufacturer's parameters to determine the best compromise option.

 

3. CONDUCTOR INDUCTANCE

When wiring components and circuits, the main obstacle to good decoupling is inductance. With very rough approximations, we can assume that the inductance of a trace with a characteristic impedance of 50 Ω on FR-4 material will be about 9 pH for every 0,025 mm of length. The inductance of a single via is approximately 500 pH and depends on the geometry.

The inductance is proportional to the length, so it is important to minimize the length of the conductor between the terminals of the component and the decoupling capacitor. Inductance is inversely proportional to trace width, so wide conductors are preferred over narrow ones.

Remember that the current path is always a loop and this loop must be minimized. Reducing the distance between the component's power pin and the capacitor's pin may not reduce the overall inductance. How to properly position the capacitor? Closer to the component's power pin? Or closer to the conclusion of the earth? Or in the middle between these conclusions? Some sources recommend placing the capacitor close to the terminal farthest from the power or ground plane.

 

4. WIRING OPTIONS OF CAPACITORS

Good wiring is extremely important for the efficient operation of decoupling circuits. As can be seen from Table 1, capacitors with an effective series inductance value of less than 1 nH are quite affordable. Adding just 2 nH will triple the ESL value of the capacitor. Figure 4 shows the change in self-resonant frequency and increase in integral reactance when adding a 2 nH conductor inductance to the 0,8 nH self-inductance of a 4,7 nF capacitor.

Decoupling strategies for PCB

Figure 5 shows several methods for placing and connecting a decoupling capacitor. For simplicity, the diagrams show only the terminals of the capacitor and the power terminal of the active component. The connection between the capacitor terminal and the component's common power terminal must also be given considerable attention.

Figure 5A shows the most common wiring configuration. The power pin of the component is connected by a short conductor to the power bus in the inner layer through a via. The decoupling capacitor on the other side of the board is connected to the same via. While this approach is often driven by ease of wiring, it allows decoupling circuits to work efficiently and saves wiring space. Two single holes will add about 1 nH of parasitic inductance to the decoupling circuit.

If the capacitor is located 50 mils (1,27 mm) from the component lead, then the added inductance will be about 0,9 nH at best. By placing the capacitor further away from the active component, the conductors will be longer and the parasitic inductance will be greater.

Decoupling strategies for PCB

Option B represents a significant improvement option A with the placement of the decoupling capacitor and the active component on the same side of the printed circuit board. The capacitor is connected after the parasitic inductance of the via. With sufficiently short conductors, the decoupling circuit adds less than 1 nH of parasitic inductance.

Option D represents the development of option A - to reduce the self-inductance and increase the distributed capacitance, the conductors are made wider, which also improves the characteristics of the decoupling circuit.

Option E - modification of option B with wider conductors and better performance.

At first glance, it seems that option C is completely unsuitable for decoupling wiring, since there are no conductors directly connecting the active component to the decoupling capacitor; in fact, they are both connected through holes to the power and ground polygons, which are located in the inner layers. With four holes, a minimum of 2 nH of parasitic inductance will be added to the decoupling circuits. However, very wide power and ground conductors will add little to no inductance if the length is not very large. This wiring option is suitable when the decoupling capacitor cannot be placed close enough to the active component.

Variant F - improvement of option C by adding additional parallel holes. This addition reduces the parasitic inductance of the vias by a factor of two, improves circuit performance, and should be used whenever space permits.

 

5. USE OF COMPOSITE CAPACITORS

Since capacitances in parallel connection add up and the resulting inductance decreases, parallel connection of two small capacitors with the same capacitance values ​​can lead to a qualitative gain compared to using a single large capacitor. The end result will be the same decoupling capacitance and less parasitic equivalent series inductance.

In practice, it is usually avoided to use capacitors with different capacitance values ​​to create a local decoupling. Composite capacitors with different capacitances have a frequency dependence of the impedance, which is made up of the frequency dependences of the impedances of individual capacitors. An example is shown in Figure 6.

Decoupling strategies for PCB

A 47nF capacitor is used to isolate low frequencies, and a 150pF capacitor is used for high frequencies. At first glance, you might think that connecting these capacitors in parallel will improve the impedance response.

Unfortunately, it is not. Such a connection can cause significant problems at frequencies that are between the natural resonant frequencies of the capacitors. Figure 7 shows that the combination of two capacitors creates an anti-resonant peak (and hence increased resistance) in the overall frequency response.

Decoupling strategies for PCB

The source of this problem is easily identified by looking at the equivalent circuit shown in Figure 8. The result of connecting parasitic capacitor components is a classic resonant circuit.

Decoupling strategies for PCB

However, compound capacitors used as decoupling elements are widely used in precision circuits. In this case, the choice of capacitors must be approached with great care, modeling circuits that include all parasitic components.

Publication: cxem.net

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