Counters. Scheme, description

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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING
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Counters. Encyclopedia of radio electronics and electrical engineering

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Encyclopedia of radio electronics and electrical engineering / Beginner radio amateur

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A counter is a device designed to count the number of pulses applied to the input. They, like shift registers, consist of a chain of flip-flops. The bit depth of the counter, and hence the number of triggers, is determined by the maximum number up to which it counts.

Counters

Fig. 1

The shift register can be turned into a ring counter if the output of the last flip-flop is connected to the input of the first. The scheme of such a counter for discharges is shown in fig. 1. Before the start of counting, the initial setting pulse in the zero bit of the counter (Q0) writes logical 1, in the remaining bits - logical 0. With the start of counting, each of the incoming counting pulses T overwrites 1 in the next trigger and the number of received pulses is determined by the output number, on which has 1. The penultimate (N-1) pulse will transfer the last trigger to a single state, and the pulse will transfer this state to the output of the zero trigger, and the count will start over. Thus, it is possible to build a ring counter with an arbitrary counting factor (any number base), changing only the number of triggers in the chain.

The disadvantage of such a counter is the large number of triggers needed; to build it. More economical, and therefore more common, counters formed by counting T-flip-flops. After each clock pulse T, the signal at input D (inverted output) changes to the opposite, and therefore the frequency of the output pulses is half the frequency of the incoming ones. By assembling a serial chain of n counting flip-flops, connecting the output of the previous flip-flop to the input C of the next), we get the frequency f_O=f_vh/2ⁿ. In this case, each input pulse changes the code of the number at the output of the counter by 1 in the range from 0 to N=2ⁿ.

Chip K155IE5 fig. 2 contains a counting flip-flop (input C1) and a divisor by eight (input C2) formed by three flip-flops connected in series. Triggers are triggered by the cutoff of the input pulse (by transition from 1 to 0). If you connect in series all four triggers as in Fig. 2, t will be a counter modulo 2⁴=16. The maximum stored number when completely filled with ones is N=2⁴-1=15=(111)₂. Such a counter works with a counting coefficient K (modulo), a multiple of an integer power of 2, and it performs a cyclic search K = 2ⁿ stable states. The counter has outputs forcing to 0.

Counters
Fig. 2

Often you need counters with a number of stable states other than 2ⁿ For example, about electronic watches, there are microcircuits with a counting factor of 6 (tens of minutes). 10 (units of minutes). 7 (days of the week). 24 (hours). To build a counter with the module K≠2ⁿ you can use a device of n triggers for which condition 2 is satisfiedⁿ>K. Obviously, such a counter can have extra stable states (2ⁿ-TO). These unnecessary states can be eliminated by using feedback, through the circuits of which the counter switches to the zero state in the cycle of operation when it counts up to the number K.

For a counter with K=10, four flip-flops are needed (since 2³<10 <2⁴) must have ten stable states N==0,1...,8,9. In the cycle when it should have moved to the eleventh stable state (N=10), it must be reset to the initial zero state. For such a counter, you can use the K155IE5 microcircuit fig. 3 by introducing feedback circuits from the counter outputs corresponding to the number 10 (i.e. 2 and 8) to the inputs of setting the counter to 0 (input R). At the very beginning of the 11th state (number 10), logical 1s appear at both inputs of the AND element of the microcircuit, generating a signal to reset all counter triggers to the zero state.

Counters
Fig. 3

In all series of digital microcircuits there are counters with the internal organization of the most common conversion factors, for example, in the K155IE2 and K155IE6 microcircuit K = 10. in the K155IE4 chip K \u2d 6x12 \uXNUMXd\uXNUMXd XNUMX.

As can be seen from the diagrams and diagrams in Fig. 1-3, counters can perform the functions of frequency dividers, i.e. devices that form from a pulse sequence with a frequency f_vh pulse sequence at the output of the last trigger with a frequency fout, K times less than the input. With this use of counters, there is no need to know what number is currently written in it, so divisors in some cases can be much simpler than counters. Chip K155IE1, for example, is a divider by 10, and K155IE8 is a divider with a variable division factor K=64/n. where n=1...63.

In addition to the considered summators, reversible counters on K155IE6 microcircuits are widely used. K155IE7, in which, depending on the mode of operation, the contents of the counter either increase by one, the addition mode, it is said that the counter increments or the subtraction mode decreases by one, decrement after the arrival of the next counting pulse. Chip K155IE1 fig. 4 - divisor by 10. Setting its triggers to 0 is carried out by simultaneously applying a high level to inputs 1 and 2 (the AND element). Counting pulses are fed to input 8 or 9 (in this case, the other input must be at a high level) or simultaneously to both inputs (element AND).

Counters
Fig. 4

The composition of the chip K155IE2 fig. 4 includes a trigger with a counting input (input C1) and a divider by 5 (input C2). When the output of the counting trigger is connected to the input C2, a binary-decimal counter is formed (the diagram of its operation is similar to that shown in Fig. 3). The account occurs on a cut of an impulse. The counter has set inputs to 0 (R0 with AND logic) and set inputs to 9 (R9 with AND logic).

Counters
Fig. 5

The K155IE4 chip is formed by a counting trigger and a divider by 6, fig. 5. The K155IE5 chip was mentioned earlier in fig. 2

Chips K155IE6 and K155IE7 fig. 6, a) - reversible counters by pre-recording, the first of them is binary decimal, the second is four-digit binary. Setting them to 0 occurs when the level at the input R is high. The counter can be written with the number of inputs to the outputs D1-D4 (in K155IE6 from 0 to 9, in K155IE7 from 0 to 15). To do this, a low level must be applied to the input S, a high level at the inputs C1 and C2, and a low level at the input R. The count will start from the recorded number by low-level pulses applied to input C1 (in addition mode) or C2 (in subtraction mode). The output information changes along the front of the counting pulse. In this case, the second counting input and input S should be high, the input R should be low, and the state of the inputs D is indifferent. Simultaneously with every tenth (sixteenth) pulse at the input C1, the output P1 repeats its output pulse, which can be input to the next counter. In the subtraction mode, simultaneously with each pulse at the input C2, which switches the counter to state 9, (15), an output pulse appears at the output P2.

The time diagram of the operation of the K155IE6 counter is shown in fig. 6b. On the diagram in the parallel recording mode (S=0), the number 6 was written (high level at the inputs D2 and D3).

Counters
Fig. 6

Microcircuits K176IE1, K56IIE10 and K561IE16 fig. 7 - binary counters. The K561IE10 counter, when counting pulses are applied to the input C1 and at C2=1, works along the front, when counting at the input C2 and at C1==0 - along the cut. The K561IE16 counter has no outputs from the second and third dividers. The counters are set to zero when a high level is applied to input R. For the correct operation of these and all other counters made using CMOS technology (series K164, K176, K564, K561 ..), it is necessary after turning on the power (or after reducing the voltage of the power supply up to 3 V) set them to the initial zero state by applying a high-level pulse to input R. Otherwise, the counters may work with random conversion factors. Reset pulse after power on can be automatically given by inputting RC timing circuit and inverter as shown in fig. 7, c.

Counters
Fig. 7

Author: -=GiG=-, gig@sibmail; Publication: cxem.net

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