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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING A simple medium wave frequency synthesizer. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / radio reception When developing this synthesizer, the authors tried to simplify its circuit and design as much as possible without sacrificing technical characteristics. The proposed synthesizer is developed in the development of an interesting topic proposed in [1]. Unfortunately, the vigorous activity of "gold miners" makes the manufacture of the synthesizer described there difficult for a wide range of radio amateurs, and when it is transferred to gold-free microcircuits in DIP packages, the dimensions of the device increase significantly. In addition, for many radio amateurs, especially beginners and those who live far from industrial centers, the production of a double-sided printed circuit board with plated holes is a difficult problem. The search for quartz resonators with low and "non-circular" frequencies does not make life easier either. The synthesizer under consideration is built according to the classical scheme with a phase locked loop (PLL) on CMOS microcircuits in gold-free packages and with a widespread 1 MHz quartz resonator. Main Specifications
The block diagram of the synthesizer is shown in fig. 1. The voltage controlled oscillator (VCO) operates at the same frequency as the output. Stability to pickups is ensured by the fact that the frequency-setting circuits of this generator do not contain inductors, and the generator itself is almost entirely located inside one microcircuit.
The pulse shaper (PI) has a single-cycle powerful output with an open drain and a permissible voltage of up to 200 V. For optimal matching with the load, the shaper provides the ability to adjust the duration of the output pulses. An exemplary reference frequency signal of 100 Hz is obtained by dividing the frequency of a crystal oscillator (KG) of 1 MHz by 10000. This frequency is chosen so low because the spectrum of the output signal of the synthesizer inevitably contains components that are separated by its value from the main output frequency. If in communication equipment this can be tolerated, then for a broadcast transmitter the presence of spectral components that create audio frequency signals during amplitude detection is unacceptable. Therefore, the comparison frequency must be chosen in the supratonal or subtonal region. In our case, the second option is adopted, since 100 Hz is easily suppressed by the receiver's post-detection filter without degrading the quality of received speech and music signals. The Frequency Phase Detector (PFD) compares a 100 Hz reference signal with a signal of the same (in capture mode) frequency, obtained by dividing the VCO frequency first by 9, and then using a variable division factor divider (CVD) by 1610-2000 in accordance with the set value of the output frequency. Depending on the sign of the mismatch of the compared signals in frequency and phase, the PFD generates a control signal that increases or decreases the frequency of the VCO. The control voltage is applied to the VCO through a proportional integrating filter (PIF) that optimizes the dynamic characteristics of the PLL. The preliminary division of the VCO frequency by 9 is dictated by two reasons. First, it is required to obtain a frequency grid with a step of 9 kHz. Secondly, the KA561IE15A chip used in the DPKD has a maximum operating frequency of 1,5 MHz.
Schematic diagram of the synthesizer is shown in fig. 2. All digital microcircuits used in it are CMOS structures of small and medium degrees of integration. Microcircuits of the K561 and KR1561 series are operable at frequencies up to 2 ... 3 MHz at a supply voltage of 3 ... 15 V. The current they consume in dynamic mode does not exceed a few milliamps. KG is made on a DD1 chip. The tuning capacitor C4 sets the generation frequency to 1 MHz with an accuracy of no worse than 1 ... 2 Hz. To obtain an exemplary signal with a frequency of 100 Hz, the pulses from the output of the KG are fed to the input C of the binary counter DD4. The K561IE16 chip used here is a 14-bit binary counter. The required division factor of 10000 is obtained using the logical node 5I on diodes VD3-VD7 and resistor R7. When, during the counting process, high logic levels are present at all counter outputs to which diodes are connected, the level at its input R will also become high, which will set the counter to its initial zero state, then the pulse counting process will be repeated. The division factor with the diode connection shown in the diagram is equal to Kд = 16+256+512+1024+8192= 10000. VCO and FFD are located in the DD2 KR1561GG1 chip. The extreme values of the VCO tuning range frequency are set by resistors R1, R2, C1. The frequency is tuned by the voltage at the IG input (pin 9 of the microcircuit). The initial data for the selection of the above elements is the frequency range of the synthesizer 1,449.1,8 MHz and the spread of VCO parameters, which can reach up to 20% from instance to instance of microcircuits. Thus, it is necessary to have a tuning margin of at least 0,36 MHz. With some margin, we will assume that the VCO should be tuned in the range of 1.2,2 MHz. The lower limit of this range (at zero voltage at the IG input) is set by resistor R2, the upper limit (at a control voltage equal to the supply voltage) is set by the total resistance of resistors R1 and R2. The operation of the VCO is enabled by a low logic level at the INH input (pin 5). The PFD has two inputs IC and IS (pins 3 and 14) and an output Q1 (pin 13). The error signal from the output Q1 through the PIF R4R3C2 is fed to the control input of the VCO IG. The PIF is a very critical part of the PLL loop. The calculation of this filter in general is quite complicated and requires knowledge of the theory of automatic control [2]. For amateur radio practice, quite satisfactory characteristics are provided by calculation using the ratios given in the reference materials for the MC14046B chip - a foreign analogue of KR1561GG1:
where N is the division factor of the operating frequency in the PLL loop; fMax and fmin - boundary frequencies of VCO tuning; 3000 Ohm - PFD output impedance. From the VCO output, the operating frequency signal is fed to the FI and the frequency divider by 9. The latter is made on the DD5 K561IE14 chip and the DD3.1 element of the K561LN2 chip. The K561IE14 four-digit reversible counter can operate as binary (high level at input B) or as decimal (low level at input B). The direction of the count is set by the level at the input U: high - increase, low - decrease. Counting pulses are fed to input C, and the state of the counter changes according to their rising drops. Counting is enabled when the PI input is low. Input S allows you to asynchronously write any eight-bit code from inputs D1-D8 to counter triggers. Since the counter of a separate input does not have an initial setting, this function is performed by input S at low levels at inputs D1-D8 (in counting up mode). The carry output goes low when the accumulated number has reached the maximum in up counting mode (or the minimum in down counting mode). In our case, the counter works to increase in decimal mode. When the tenth pulse arrives, the signal from the transfer output through the inverter DD3.1 forcibly sets the counter to zero. From output 4 of the counter, the signal goes to the DPKD - chip DD6 KA561IE15A. It has counting pulse input C, four control inputs K1, K2, K3, L, sixteen 1-8000 inputs for setting the division factor, and one output. The division factor can be in the range 3-21327, and there are several ways to set it. The synthesizer uses the simplest and most convenient way - the coefficient is set by a binary-decimal code applied to the inputs 1-8000. In this case, however, its maximum possible value is 16659. To use this method, the inputs K1 and L must be set to different logic levels (low and high or high and low), and the input K3 must be set low. Input K2 serves to set the counter to the initial state, which occurs at a low level at this input for three periods of counting pulses. At a high level on it, the counter operates in the frequency divider mode. The desired levels at the inputs 1-8000 are set by the switch SA1 and SA2. Their contacts, connected to a common wire, correspond to low levels at the corresponding inputs of the microcircuit, and free ones to high levels (they are supported by resistors R8-R15). The FI allows you to set the duration of the output pulses, which is optimal for the load connected to the synthesizer, for example, the output circuit without intermediate amplifiers (as in the transmitter, the circuit of which is given in [3]). FI is built on logical inverters DD3.2-DD3.6, diode VD2, trimmer resistor R6, transistors VT1-VT3. The emitter follower on transistors VT1 and VT2 reduces the duration of charging and discharging the capacitance of the gate of the field-effect transistor VT3, thereby increasing the speed of turning it on and off. The charging of the input capacitance of the elements DD3.3-DD3.6 occurs quickly through the low dynamic resistance of the VD2 diode, and the discharge is relatively slow through the tuning resistor R6. The duration of the discharge, and due to this, the duration of the generated pulse depends on the input resistance of the resistor R6. On the design and adjustment of the synthesizer The synthesizer is made on a single-sided printed circuit board 1,5 mm thick (Fig. 3).
It is made by thermal transfer of the conductor pattern onto the foil surface from its printout on a laser printer. The numbers of the mounting holes on the board, intended for the wires going to the switches, match the wire numbers of the harness in the diagram. It is advisable to install mounting pins in these holes, as well as in those intended for power and load wires. Transistor VT3 and voltage regulator DA1 are located on a common heat sink (do not forget to lubricate their seats with heat-conducting paste KPT-8), made of aluminum sheet according to the drawing shown in fig. 4. Transistor VT3 must be installed on the heat sink through an insulating gasket. The long arm of the heat sink is fixed on the board with a wire clamp.
Fixed resistors - MLT or similar. Trimmer resistor R6 - SP3-38a. Capacitor C2 (it can be, for example, K73-24) must be with an organic dielectric. Capacitor C4 - trimmer KT4-24. Capacitors C1, C3, C7-C10 - any ceramic suitable size. Oxide capacitors are also any suitable in size and rated voltage.
The KA561IE15A chip can be replaced with the 564IE15, but unfortunately it is more expensive because it contains gold. It is such a microcircuit that is installed in the synthesizer shown in the photograph in Fig. 5. Instead of K561LA7, K561LE5 will work without changing the circuit and board. Transistors VT1, VT2 - any low-power silicon of the appropriate structure. Switches SA1 and SA2 - P2G-3, respectively, 4P4N and 10P4N or any other biscuit, suitable for the number of positions and directions. Quartz resonator - RG-06 or RK170. Accurately assembled from known good elements, the synthesizer does not require adjustment, it is only necessary to set the frequency of the quartz oscillator with a trimmer capacitor C4 with an accuracy of ± 2 Hz. It is controlled at pin 11 of the DD1 chip. The tuning resistor R6 is used to achieve the maximum undistorted carrier signal on the antenna equivalent. PS In a transmitter with a power amplifier, the synthesizer board must be well shielded to prevent interference with the VCO, which can lead to PLL malfunctions. Literature
Authors: E. Golomazov, M. Doutaliev, B. Kanaev
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