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New opportunities for overclocking 7nm chips

15.08.2020

As the scale of the chip manufacturing process decreases, not only the size of transistors decreases, but also the accompanying "infrastructure", for example, the diameter of the holes for creating vertical contacts. Such contacts are made from tungsten in a metallization process, and their resistance increases as technology standards decrease, which reduces the performance and energy efficiency of the chips. But it managed to get around.

The reserve was opened by Applied Materials. The fact is that modern technical processes involve the deposition of tungsten from a vapor medium onto metallization holes specially prepared for this. Before deposition (filling the holes with tungsten), a layer of titanium nitride is deposited on the chip surface and on the walls of the holes in the dielectric layer. This substance improves the "sticking" of tungsten to the walls of the holes for vertical contacts, protects the crystal from contamination by fluorine, which is used in the deposition process, and finally aligns the walls of the holes.

Applied Materials' new process and splice plating machine fills dielectric holes with tungsten from the bottom instead of the top (video below). The company called it "selective gap filling." Since new materials and technologies are used for this, it is no longer necessary to protect the crystal from fluorine, as well as to improve the adhesion of tungsten to the walls of vertical holes.

The proposed technology reduces the resistance of vertical connections by 40%, and in fact, up to 300 kilometers of such connections are laid in each 100-mm silicon wafer with chips. The benefits of using the new technology promise to be very, very impressive.

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