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Single transistor SRAM cell architecture

18.12.2015

At the International Electron Devices Meeting 2015, Zeno Semiconductor unveiled a bipolar NMOS transistor, which, upon closer examination, turned out to be composed of two open-base transistor structures. It turned out to be a kind of virtual transistor with the ability to work like a two-transistor SRAM cell.

The developer proposes to create energy-efficient single-transistor SRAM cells and productive two-transistor cells from such transistors. In both cases, the area of the SRAM Zeno cell will be several times smaller than the area of \u6b\uXNUMXbthe classic XNUMXT-SRAM. This saves space and energy consumption, including the benefit of reducing leakage.

The cell area of SRAM Zeno in the 28nm process is reported to be 0,025 square meters. µm. A typical 6T-SRAM in this process is 0,127 square meters. µm. Interestingly, the new cell is even smaller than Samsung's 10nm FinFET SRAM with an area of 0,040 square meters. µm.

The developers also report that the reliability of the innovative single-transistor cell will be no worse than the SEU (Single Event Upsets) for 6T-SRAM.

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