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Multi-level ROM memory cells

28.06.2013

Toshiba and TSMC have developed an MROM (read-only) memory mask that has a high data density by storing a few bits per cell.

Conventionally, the ROM mask is formed by the intersection of a single word and bit lines and stores a single bit in a cell, depending on whether the diode connects them or not. However, due to the instability of the manufacturing process in advanced technologies and the narrowing of the cell transistor channel area, the access time in the 40nm process is increased compared to the previous generation of processes.

At the VLSI Circuits Symposium last week in Kyoto, Japan, Toshiba announced that it has developed a multi-bit cell that covers twice the area of a standard single-level cell.

The article considers a three-wire programmable cell (TWPC), which consists of a single transistor with three bit lines and stores two bits of data in the cell. Toshiba released memory in a 40nm process in a 1Mbit test chip and reported a 38% improvement in access time through the use of TWPC. Power consumption in active mode and standby mode is kept at the same level as a standard cell. The circuit also triples the operating characteristics of the cell without any change in memory capacity per unit area. This reduces the impact of instability in the manufacturing process by 42%, Toshiba said.

The main purpose of an MROM is to store downloadable data or organize ROMs that can then, when the hardware is turned on, load other software from the non-volatile memory. However, the amount of MROM required for system-on-a-chip applications is increasing for devices such as smartphones and tablet computers.

Toshiba said the company aims to bring to market SoCs for digital applications in 2014 that implement a multi-bit MROM cell. However, in an article following Toshiba's announcement, foundry chip supplier TSMC said it had created a two-bit ROM cell using a 28nm process. The article considers a two-step decoding scheme that is suitable for single-wire or differential reading. TSMC reported that their 28nm low-power process design improves access time by 30% and is powered by 190mV less voltage.

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