New power modules of the SPM series. Free Technical Library News

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New SPM Series Power Modules

19.03.2006

FAIRCHILD SEMICONDUCTOR introduces three new SPM series power modules designed for power factor correction of electric motors in the power range from 3 to 6 kW.

Chips FPDB20PH60 (600V/20A), FPDB30PH60 (600V/30A), FPDB50PH60 (600V/50A) allow you to get a power factor of 99% and save 50% of space compared to discrete solutions. Available in 44x26mm MiniDIP packages with lead-free technology.

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SRAM Chips Renesas RMLV0816B and RMLV0808B with high radiation hardness 21.12.2014

Renesas Electronics has announced the release of five new low power static random access memory (Advanced LP SRAM) chips in the RMLV0816B and RMLV0808B series. They have a density of 8 Mbit and are manufactured according to the standards of 110 nm.

Why use such a "rough" technical process, when microcircuits for consumer mobile electronics have long been produced according to much finer standards?

The thing is that by increasing the elements, it is possible to increase the radiation resistance. According to the manufacturer, single failures (Soft Error or Single-Event Upset, SEU) and transistor latch-up (Latch-up) are excluded in the new memory.

The cause of single failures is the current pulse that occurs when an ion enters the cell. It puts the cell in the opposite state, but the circuit remains in a healthy state. Since the size of the transistor in the new chips is relatively large, switching requires such a large charge that the probability of a failure tends to be zero. In addition, a special capacitor is introduced into the cell circuit. Unlike ECC error correction, this approach prevents multiple errors from occurring at the same time. The use of this and other techniques, according to Renesas, made it possible to obtain the same degree of radiation resistance as in the case of microcircuits manufactured according to 150 nm standards.

As for transistor latching, it is caused by an ion-induced current pulse, which leads to the opening of a thyristor-like circuit formed by parasitic structures from pairs of transistors of different types. As a result of latch-up, the current through the transistors increases even after the ion exposure stops, which can lead to overheating and failure of the microcircuit. In the new memory, only n-channel transistors are formed on a single-crystal substrate, and p-channel transistors are formed as thin-film transistors using polycrystalline silicon, which eliminates the formation of a thyristor from parasitic structures and fundamentally eliminates the risk of transistor snapping. Along the way, this made it possible to reduce the cell area and the size of the crystal, bringing these indicators closer to those of memory produced according to 65 nm standards.

The standby current consumption is less than 2µA at 25°C, making the chips suitable for data storage in battery-backed devices.

Renesas plans to release such memory with a density of 16 Mbps.

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