SAMSUNG FLASH memory chips. Reference data

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SAMSUNG FLASH memory chips. Reference data

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Encyclopedia of radio electronics and electrical engineering / Application of microcircuits

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The article describes 4 Gbit flash memory chips K9K4G08Q0M-YCB0/YIB0, K9K4G16Q0M- YCBO/YIBO, K9K4G08U0M- YCBO/YIBO, K9K4G16U0M-YCB0/YIB0. These microcircuits are used as non-volatile memory in consumer, industrial and computer devices. In digital video and photo cameras, voice recorders and answering machines, these chips are used as memory for image and sound as part of solid-state flash drives.

Flash memory chips are divided into groups according to supply voltage and architecture (Table 1). In table. 2 shows the pin assignment of flash memory chips.

Table 1

Device designation	Supply voltage (nominal value)	Architecture	Type of shell
K9K4G08Q0M-Y	1,70...1,95V(1,8V)	512 Mbps x 8	TS0P1
K9K4G16Q0M-Y	1,70...1,95 V (1,8 V)	256 Mbps x 16	TS0P1
K9K4G08U0M-Y	2,7...3,6 V (3,3 V)	512 Mbps x 8	TS0P1
K9K4G16U0M-Y	2,7...3,6 V (3,3 V)	256 Mbps x 16	TS0P1

Table 2

No. of pins	Pin designation (chip type)	Pin assignment
29-32; 41-44	I/O(0-7) (K9K4G08X0M-Y)	Data input/output. Pins are used to input/output cell addresses, data or commands during read/write cycles. When a chip is not selected, or pins are disabled, they are placed in a high impedance state.
26, 28, 30, 32, 40, 42, 44, 46, 27, 29, 31, 33, 41, 43, 45, 47	I/0(0-15) (K9K4G16X0M-Y)
16	Thanks	Command commit permission. A high signal level on this pin switches the multiplexers on the I / O inputs in the direction of the command register. The command is written to the register at the edge of the signal WE
17	SALE	Address fixing permission. A high signal level at this input switches the multiplexers on the I / O inputs in the direction of the address register. Bend the command into the register is made on the edge of the signal WE
9	CE	Chip selection. A low level at the input allows the data read operation, and a high level, in the absence of any operations, puts the chip into standby mode. During write/erase operations, the high level on this input is ignored.
8	RE	Read permission. The input controls the serial data output when data transfer is active on the I/O bus. The data is valid after the fall of the RE signal and some normalized sampling time. The RE signal also increments the column's internal address counter by one.
18	WE	Recording permission. The input controls writing to the I/O port. Commands, address and data are latched on the edge of WE
19	WP	Write lock. The output provides protection against accidental writing/erasing during power-up. The internal programming voltage generator is disabled when the WP pin is active low.
7	R/B	Free/busy. The R/B output indicates the state of the chip. A low level indicates that a random access write, erase, or read operation is in progress, and a high level is set when these operations are completed. This open-drain output does not transition to a high impedance state when the chip is not selected, or when the outputs are disabled.
38	PRE	Read permission at power on. The PRE output controls the auto-read operation performed at power-up. Power-on autoread is enabled if the PRE pin is connected to the VCC pin.
12	VCC	Supply voltage
13	VSS	General

The K9K4GXXX0M chips have a capacity of 4 Gb with 128 Mb of reserve (actual capacity is 4 bits) and a 429 Mb x 185 or 024 Mb x 512 architecture with up to 8M write/erase cycles reliability. 256-bit chips are organized in 16 x 1 pages, while 8-bit chips are organized in 2112 x 8 columns. All microcircuits have spare bits located in 16 rows with addresses 1056-16 for 128-bit microcircuits, or in 2048 columns with addresses 2111-8 for 64-bit microcircuits. To organize data transfer during a page read / write operation between memory cells and I / O ports, these microcircuits have data registers 1024 bytes in size for an 1055-bit microcircuit, or 16-word for a 2112-bit microcircuit and registers connected in series with each other cache of the appropriate size. The memory array is built from 8 connected cells located on different pages and united by a NAND structure. 1056 cells that combine 16 32I-NOT structures and are located on 32 pages make up a block. A collection of 135168- or 2-bit blocks constitutes a memory array.

The read operation is performed page by page, while the erase operation is only block by block: 2048 individually erased 128 KB ps blocks (for 8-bit microcircuits), or 64 Kword blocks (for 16-bit microcircuits). Erasing individual bits is not possible.

Writing a page to microcircuits is performed in 300 μs, erasing - in 2 ms per block (128 KB for 8-bit microcircuits, or 64 Kwords for 16-bit microcircuits). A byte of data is read from a page in 50 ns.

To record and control data in microchips, there is a built-in controller that provides the entire process, including, if necessary, repeating the operations of internal verification and data labeling. The K9K4GXXX0M microcircuits have a system for providing information verification with error correction and culling of erroneous data in real time.

Chips have 8 or 16 multiplex I/O addresses. This solution drastically reduces the number of outputs involved, and allows for subsequent upgrades of devices without increasing their size. Commands, addresses and data are entered at a low level at the CE pin by the fall of the WE signal through the same input / output pins. The input information is written to the buffer registers on the rising edge of the WE signal. The command write enable (CLE) and address write enable (ALE) signals are used to multiplex the command and address, respectively, through the same I/O pins.

Table 3

Operation	HEX code 1st cycle	HEX code 2st cycle
Reading	00	30
Read to overwrite	00	35
Reading a signature	90	-
Reset	FF	-
Write per page	80	10
Write to cache	80	15
Rewriting	85	10
Block erasing	60	DO
Free data entry*	85	-
Free data output*	05	E0
Reading Status	70	-

* Arbitrary input / output of data is possible within one page

In table. 3 shows the control commands of the microcircuits. Submission to the inputs of other, not listed in the table, hexadecimal (HEX) command codes leads to unpredictable consequences, and therefore is prohibited.

To improve write speed when receiving large amounts of data, the onboard controller has the ability to write data to cache registers. When the power is turned on, the built-in controller automatically provides access to the memory array, starting from the first page without entering a command and address. In addition to the improved architecture and interface, the controller has the ability to copy (overwrite) the contents of one memory page to another without accessing external buffer memory. In this case, the data transfer speed is faster than in normal operation, since there are no time-consuming sequential accesses and data entry cycles.

Block culling

Memory blocks in the K9K4GXXX0M chips are defined as invalid if they contain one or more invalid bits that cannot be read unambiguously. Information from invalid blocks is treated as "invalid block information". Chips with invalid blocks do not differ in static and dynamic characteristics and have the same quality level as chips with all the correct blocks. Invalid blocks do not affect the operation of normal blocks because they are isolated from the bit and common supply rail by the selection transistor. The system is designed in such a way that addresses are blocked for invalid blocks. Accordingly, there is simply no access to incorrect bits.

Invalid Block Identification

The contents of all microcircuit cells (except those where information about invalid blocks is stored) with addresses FFh for 8-bit and FFFFh for 16-bit can be erased. The addresses of invalid blocks located in the spare area of the memory array are determined by the first byte for 8-bit chips or the first word for 16-bit ones. The manufacturer guarantees that either the 1st or 2nd page of each block with addresses of invalid cells has data in columns with addresses 2048 (for 8-bit) or 1024 (for 16-bit) that is different from FFh or FFFFh, respectively. Since information about invalid blocks is also erasable, in most cases, erasing the addresses of bad blocks cannot be restored. Therefore, the system must have an algorithm capable of creating a table of invalid blocks, protected from erasure and based on the initial information about bad blocks.

After clearing the memory array, the addresses of these blocks are loaded again from this table. Any intentional erasure of the original information about invalid blocks is prohibited, as it leads to incorrect operation of the system as a whole.

Over time, the number of invalid blocks can increase, so you should periodically check the actual memory capacity by checking the addresses of the invalid blocks against the data in the backup invalid block table. For systems that require high fault tolerance, it is best to provide for the possibility of block-by-block rewriting of a memory array with a comparison of the results with actual data, quickly identifying and replacing blocks of incorrect information. The data from the detected invalid block is transferred to another, normal empty block, without affecting neighboring blocks of the array and using the built-in buffer, the size of which corresponds to the size of the block. For this, commands for block-by-block rewriting are provided.

Publication: cxem.net

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