Modern FPGAs from XILINX: VIRTEX series. Reference data

Encyclopedia of radio electronics and electrical engineering / Application of microcircuits

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In 2014, the American company Xilinx celebrates its 30th anniversary. Already at an early stage of its existence, in 1984, the company proposed a new type of logic circuits - user-reprogrammable basic matrix crystals (Field Programmable Gate Array, or FPGA). ICs have given the electronics designer the benefits of standard basic matrix crystals while allowing the design, configuration, debugging, bug fixing, and reconfiguration of the IC on the job site. As a result, the flexibility of the device has improved and the time to market of finished products has been significantly reduced. What are the achievements of Xilinx to date?

Introduction

Today, Xilinx releases several series of FPGAs. They are divided into FPGA - user-reprogrammable basic matrix crystals - and CPLD (Complex Programmable Logic Devices) - complex programmable logic devices. In each series - from one to several families, containing, in turn, microcircuits that differ in capacity, speed, and package type (see figure). The main features of Xilinx FPGAs (as of early 2004):

• a significant amount of resources: more than 10 million system gates per chip;
• high performance: system frequencies over 400 MHz;
• promising manufacturing technology: topological standards up to 90 nm, nine-layer metallization, including copper;
• highly flexible architecture with many system features: internal distributed and block RAM, fast transfer logic, third-state internal buffers, etc.;
• possibility of initialization and verification via JTAG;
• possibility of programming directly in the system;
• a wide range of products: from inexpensive and relatively simple microcircuits for implementing large-scale logic projects to very complex ones for creating high-speed digital signal processing tools, modeling and prototyping of new types of processors, computing devices, etc.;
• short design cycle and low compilation time;
• inexpensive design tools (including free ones).

Xilinx produces FPGAs based on three types of memory:

• SRAM (FPGA-type). In this case, the circuit configuration is stored in the internal, "shadow", RAM, and initialization is carried out from an external memory array. The configuration sequence (bitstream) can be loaded into the FPGA directly in the system and reloaded an unlimited number of times. Initialization of the FPGA is performed automatically from the external boot ROM when the supply voltage is applied or forced by a special signal. The initialization process takes 20-200 ms, during which the FPGA pins are in a high-resistance state (pulled up to a logical unit). FPGAs of this type include chips of the Virtex, Spartan series;
• flash memory. The configuration is stored in the internal non-volatile flash memory and can be overwritten at any time directly from a PC via the JTAG port, eliminating the need for a programmer. Through JTAG, internal testing of the circuit is also provided. This technology is used for CPLDs of the XC9500 family;
• EEPROM. In such FPGAs, the configuration is stored in an internal non-volatile EEPROM, and at any time it can be overwritten directly from the PC. CPLDs of the CoolRunner family are made using this technology.

During the debug phase, the configuration can be downloaded from a computer using three types of cables: MultiPRO Desktop Tool, Parallel Cable IV and MultiLinx Cable. All cables support CPLD chip programming no JTAG port. When choosing a cable, it is necessary to take into account their properties, given below:

MultiPRO Desktop Tool connects to a PC parallel port, supports in-system programming / configuration of all Xilinx FPGAs, as well as offline programming of CoolRunner-ll family FPGAs and XC18V00 and PlatformFlash series PROMs. At the same time, the presence in one set of both the programmer itself and the download cable made it possible to reduce the cost of a set of tools for debugging and programming;

Parallel Cable IV connects to PC parallel port, supports FPGA boot and CPLD programming, and configuration readback via JTAG port. The supply voltage is supplied from an external 5-V source. The delivery of the cable includes an adapter designed to supply voltage to the cable from the PS / 2 port of the computer;

MultiLinx Cable connects to the RS-232 port of a PC or workstation, as well as to the USB port of a PC. The supply voltage (5; 3,3; 2,5 V) is supplied from the board.

Rice. 1. Xilinx FPGA

Xilinx offers a complete set of software that allows you to implement a project based on the released FPGAs. The software includes schematic and text input, VHDL/Verilog synthesis, functional simulation, crystal tracer, post-trace simulation, and more. In addition, Xilinx develops specialized modules, the so-called logical cores, which can be used as library elements when designing FPGA-based devices.

Brief classification of modern XILINX microcircuits

To date, the following Xilinx FPGAs are the most promising:

• FPGA series Virtex;
• FPGA of the Spartan series, with the exception of chips of the Spartan (supply voltage 5 V) and Spartan-XL (3,3 V) families;
• CPLD XC9500 series;
• CoolRunner-ll series CPLD.

The use of other Xilinx FPGA series currently being produced in new developments is not recommended. Therefore, we will not consider them.

VIRTEX series

The FPGA series includes four families: Virtex, Virtex-E, Virtex-ll and Virtex-ll Pro. Released in late 1998, the Virtex series extended the traditional FPGA-type FPGAs with a powerful set of features to solve high-performance system design challenges. FPGA-chips of the series are characterized by a flexible architecture, consisting of a matrix of configurable logic blocks (Configurable Logic Blocks - CLB), surrounded by programmable I / O blocks (Input-Output Blocks - SE). Dedicated overdrive logic for high-speed arithmetic, dedicated multiplier support, cascadable chains for high-input functions, multiple clock-enabled registers/latches with synchronous/asynchronous reset and set, internal tri-state buses balance speed and logic packing density .

The hierarchical system of memory elements of the series microcircuits includes: distributed memory based on four-input look-up tables (4-LUT - Look-Up Table), configured either as a 16-bit RAM or a 16-bit shift register; built-in block memory (each block is configured as synchronous dual-port RAM) and interfaces to external memory modules. FPGAs of the series support most I/O standards (SelectIO™ technology), and FPGAs of later families support differential signal transmission standards - LVDS (Low-Voltage Differential Signaling), BLVDS (Bus LVDS), LVPECL (Low-Voltage Positive Emitter-Coupled Logic ). High-speed built-in timing control circuits are provided. The design is carried out using the ISE (Integrated Software Environment) software package running on a PC or workstation: ISE BaseX, ISE Foundation, ISE Alliance. Chips of the Virtex series are produced with topological norms of 0,22-0,15 microns and multilayer metallization. All microcircuits of the series are 100% factory tested.

Let's take a closer look at the main families of microcircuits included in the Virtex series.

Virtex family - the fourth generation of FPGA chips after the release in 1984 of the first FPGA of this type. For the first time, FPGA microcircuits of the family made it possible to implement not only ordinary logic functions, but also operations that are still performed by separate specialized products. With the advent of the Virtex family, FPGAs have moved from the category of interconnecting logic circuits to the category of programmable devices that serve as the center of digital systems.

The main features of the Virtex family of FPGAs are: high performance (up to 200 MHz), large logical capacity (50 thousand-1 million system gates), core supply voltage 2,5 V, compatibility with the 66 MHz PCI bus, support for the "hot swap" function for Compact PCI (Table 1). The family chips support 16 high-performance I/O standards, including LVTTL, LVCMOS2, PCI33, PCI66, GTL/GTL+, SSTL, HSTL, AGP, and CTT, as well as direct connection to KZBTRAM devices. The built-in clock control circuits include four built-in DLL-Delay-Locked Loop modules and four wide-area clock distribution networks with low edge times plus 24 local clock networks. Each block of onboard memory is configured as synchronous dual-port 4Kb RAM (maximum total capacity 128Kb).

Table 1. Parameters of microcircuits of the Virtex family

Microcircuits of the family are manufactured according to 0,22-micron CMOS technology with five-layer metallization.

Virtex-E family, released already in September 1999, is comparable in its characteristics and properties to specialized ASICs. FPGA chips of the family are designed for data exchange and digital signal processing systems. Compared to microcircuits of the first family, they are characterized by higher performance (system frequency up to 320 MHz) and greater logical capacity (over 2 million system gates, Table 2). Like the previous family, SelectIO™ technology provides support for multiple I/O standards, including, for the first time, differential transmission standards - LVDS, BLVDS, LVPECL. The chips of the family support 32/64-bit, 33/66-MHz PCI. The core supply voltage is 1,8 V. The hierarchical three-level memory system is the same in structure as in the previous family. But the maximum capacity of block memory has been increased by 8,75 times - up to 1120 kbit. There are also fast interfaces to external high performance RAM such as 200MHz ZBTSRAM and 200Mbps DDR SDRAM.
The emergence of the Virtex-E family of chips was made possible by the transition from 0,22 µm CMOS technology with five-layer metallization to 0,18 µm processes and six-layer metallization.

Thus, in the microcircuits of this family, in comparison with Virtex, the following are increased:

• equivalent logical capacity (three times);
• number of supported I/O standards (from 17 to 20);
• the maximum number of user input-output contacts (by 1,5 times, from 512 to 804);
• performance of I/O units (1,5 times - from 200 to 320 MHz);
• number of built-in latency auto-tuning modules - DLL-modules (twice - from four to eight);
• number of user I/O blocks (up to 560).

Table 2. Virtex-E Family Chip Parameters

Many high performance networking and imaging systems require large amounts of RAM. In response, Xilinx released a larger memory version of the Virtex-E family in early 2000, the Virtex-EM (XCV504E and XCV812E).

Table 3. Parameters of chips with increased block memory capacity of the Virtex-EM family

These microcircuits are an efficient and reliable platform for building switching systems with a transmission rate of 160 Gbit / s (Table 3). The high throughput was achieved by increasing the size of the two-port block memory to 1 Mbit and using two layers (upper and clock signal distribution) in the six-layer metallization, made using copper technology.

Virtex II family implements a new ideology for the formation of FPGA platforms, which allows FPGAs to become the main component of a digital device. On one chip of the Virtex-ll family, you can create a complex digital system with a logical capacity of up to 8 million system gates. At the same time, in comparison with a custom-made integrated circuit of the same functionality, the development time is significantly reduced. The Virtex-ll family includes 11 microcircuits that differ in logical capacity (Table 4).

Table 4. Main parameters of the FPGA of the Virtex-ll family

The family is suitable for the design of a wide class of low and high integration high performance systems such as data communication devices and digital signal processing devices. Chips of the Virtex-ll family implement complete solutions in the field of telecommunications, network systems, wireless communications, digital signal processing using interfaces with PCI, LVDS and DDR. An example of such solutions is the implementation of PowerPC 405 and MicroBlaze processors. The CMOS technology used for the production of microcircuits with topological norms of 0,12-0,15 microns and eight layers of metallization makes it possible to implement projects with high speed and low power consumption.

The logical capacity of microcircuits of the Virtex-ll family is 40 thousand-8 million system gates on a chip, the internal clock frequency exceeds 400 MHz, the data exchange rate is more than 840 Mbps per one input-output pin. The amount of distributed memory reaches 1,5 Mbit, the built-in memory, implemented on blocks of dual-port RAM with a capacity of 18 kbit each, is 3 Mbit. Interfaces to external memory modules such as DDR-SDRAM, QDR™-SRAM and Sigma RAM are provided.

The family microcircuits contain multiplier blocks 18x18 bits, up to 93184 registers / latches with clock enable and synchronous / asynchronous reset and set, and 93184 function generators (4-LUTs). Timing control is provided by up to 12 timing control modules (DCMs) and 16 global clock multiplexers. Provides fine-tuning of clock edges, frequency multiplication, frequency division, high-resolution phase shift, and EMI protection.

The Active Interconnect technology used makes it possible to obtain a fourth-generation segmented routing structure with predictable delays that do not depend on the output fanout factor.

Up to 1108 user-programmable I/O blocks, 19 single-pole and six differential I/O standards support most digital signal standards. Built-in double data rate input and output registers provide LVDS signaling at 840 Mbps. Programmable current capacity - 2-24 mA per output.

The impedance of each I/O block is programmable. Virtex-ll chips are compatible with PCI-133/66/33 MHz buses. There are five configuration loading modes. Encryption of the configuration sequence is carried out according to the TRIPLE DES standard, configuration support - according to the IEEE 1532 standard. Partial reconfiguration is possible. The supply voltage of the crystal core is 1,5 V, the input-output units - 1,5-3,3 V, depending on the programmed signal standard.

Chips are manufactured using CMOS technology with design standards of 0,15 µm (the channel length of high-speed transistors is 0,12 µm) and eight layers of metallization.

Virtex-ll Pro family is designed to create systems based on intelligent IP cores and custom parameterizable modules. The microcircuits of the family are optimized for the implementation of complete solutions in the field of telecommunications, wireless communications, networking, video and digital signal processing. For the first time, the chip architecture features RocketIO multi-bit transceivers and PowerPC processor cores. They are manufactured using CMOS technology with a topological norm of 0,13 microns and a nine-layer copper metallization, which made it possible to reduce the size of the crystal and power consumption compared to the chips of the previous series.

Table 5. Main parameters of the FPGA of the Virtex-ll Pro family

The architecture of Virtex-ll and Virtex-ll Pro matrices is the same. Most of the technical characteristics also coincide (Table 5). The differences between the chips of the two families are as follows:

• lower limit value of the peripheral supply voltage: 2,5 V vs. 3,3 V for the Virtex-ll series;
• higher performance of Virtex-ll Pro;
• different pinout and configuration sequence, although designs made on Virtex-ll series chips can be transferred to Virtex-ll Pro chips;

The Virtex-ll Pro series is the first FPGA family of FPGAs to feature built-in RocketIO transceivers and PPC405 processor cores.

RocketIO is a full duplex serial transceiver (SERDES) supporting connections from 2 to 24 channels with bandwidths from 622 Mbps to 3,125 Gbps. Bidirectional data transfer rate -120 GB / s. In each channel, an internal feedback loop is possible. The transceiver has features such as built-in clock generation and recovery (CDR), frequency equalization by character insertion/deletion, programmable comma delimitation, 8-, 16-, or 32-bit internal interface, 8-/10-bit encoder, and decoder. RocketIO is compatible with Fiber Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI) transmission protocols, and broadband transceivers. User configurable internal receiver/transmitter terminations are 50/75 ohms. Five levels of output differential voltage are provided, four levels of pre-emphasis are selectable. Transceiver supply voltage 2,5 V.

The PowerPC processor unit is an embedded core with a clock frequency of up to 400 MHz with a Harvard architecture, a five-stage pipeline data transmission path, and hardware multiply/divide. The block also contains thirty-two 32-bit general-purpose registers, associative bidirectional instruction and data caches with a capacity of 16 Kb each, a memory management block, 64-input Translation Look Aside Buffers (TLBs), an on-board special memory interface . Page sizes can vary from 1K to 16 Mbps. There is a built-in timer. The processor unit supports the IBM CoreConnect bus architecture, debug and trace operations. Its power consumption is low: 0,9 mW/MHz.

Virtex series FPGA based on advanced industrial technology, featuring high performance and cost efficiency, is one of the main types of programmable logic circuits used by developers around the world. And since their release in March 2002, Xilinx has shipped over 100 PowerPC cores based on Virtex-ll Pro FPGA chips.

Author: M. Kuzelin; Publication: cxem.net

See other articles Section Application of microcircuits.

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