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ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING Video processors of the TDA88xx series. Reference data
Encyclopedia of radio electronics and electrical engineering / Reference materials The first video processors of the TDA8362 series for a single-chip TV, released by Philips in 1991, used analog operational adjustments. Additional chips were required to decode the SECAM signal and delay the color difference signals. In addition, an external resonant circuit was needed to demodulate the radio signal and form the signal of the APCG system. And yet, despite such an imperfection of the TDA8362 series microcircuits, they were used very widely, since they made it possible to significantly reduce the total number of attachments. The improvement of the single-chip video processor was aimed at improving its parameters and further reducing the number of external elements. Already in the next series (TDA837x), a radio signal demodulator was introduced into the video processors in the form of a PLL system with an external loop, which is part of the VCO and tuned to a double image IF. Instead of analog adjustments, they use 12C digital bus control. In 1997, the company's specialists developed a series of TDA88xx video processors. In UPCHI, the outer contour is excluded. Tuning the VCO to the desired frequency is provided via a digital bus. It is possible to demodulate radio signals with both negative and positive modulation. A SECAM signal demodulator has been introduced into the microcircuits. chrominance signal delay line, adjustable delay line and tunable notch filter in the luminance channel, luminance signal edge sharpening device, dark current auto-balance device, auto-balance device in white. It also provides for obtaining a blue raster in the absence of a signal, automatic switching off of horizontal scanning in case of malfunctions, and the ability to adjust the geometry of the raster via a digital bus. In the sound channel, automatic volume stabilization has been introduced, which ensures its equal level when receiving stations with different modulation coefficients. It is possible to change the size of the raster vertically and horizontally via a digital bus, which makes it possible to observe images of 4:3 and 16:9 standards on kinescopes of various formats. For NTSC TVs, the color of human skin is automatically adjusted. The new series of single-chip video processors provides for the possibility of producing a wide range of TV sets based on a standard chassis, starting with a relatively simple device on a kinescope with a beam deflection angle of 90, monophonic sound and two color systems of the received signal, and ending with expensive television receivers on kinescopes with 110 ° deflection and 16 format: 9. receiving programs in several television RF and color standards. In TVs intended for use in Russia, from the entire series of TDA88xx video processors, the TDA8842 chip (a simple SECAM-PAL TV with a 90 ° kinescope) is suitable for use. TDA8844 (multi-standard annapai with a 110" kinescope and the possibility of introducing circuits that improve the quality of a color image: a comb filter, an optimizer of gradation characteristics of the luminance channel, etc.) and TDA8854 with two additional inputs of external signals RG B, as well as an additional output of a composite video signal, designed, for example, for the block "frame in the frame" (PIP). The TDA8842 and TDA8844 microcircuits are produced in an SDIP package with 56 pins, and the TDA8854 chip is in a QFP-64 package (it has 64 pins) designed for surface mounting. A simplified block diagram of the TDA8844 video processor with its accompanying external circuits is shown in fig. 1.
The IF radio signal comes from the channel selector through the SAW filter and the symmetrical input of the microcircuit (pins 48, 49) into the radio channel. A detailed block diagram of the radio channel is shown in fig. 2. The input signal is amplified by a three-stage adjustable UPHI. The gain margin is 64 dB. The typical sensitivity of the radio channel is 70 µV. It can be reduced via the digital bus (by the IFS bit) by 20 dB.
After amplification, the signal is demodulated by a synchronous detector, in which a double frequency reference signal is generated in the PLL without the use of an outer loop. The initial VCO frequency is regulated inside the microcircuit via a digital bus (IFA, IFB, IFC bits). In this case, one of the quartz resonators of the color decoder is used for calibration. The PLL capture bandwidth is ±1 MHz. The PLL bandpass filter time constant is changed by the FFI bit. During demodulation, the signal is multiplied by the reference signal. UPCHI is covered by a key-type AGC system loop. A special node with an adjustable delay generates the AGC voltage for the channel selector. The delay value is determined by the TOP0 - TOP5 bits, which corresponds to an input signal of 0,4...80 mV. The AGC voltage is taken from the open collector transistor and output through pin 54. The chip allows you to process radio signals with both negative and positive modulation (switching occurs via a digital bus with the MOD bit supplied to the demodulator and AGC detector). With positive modulation, the key pulses of the AGC system are the pulses generated in the processor in the blanking intervals over the fields, the amplitude of which corresponds to a white level of 100%. These pulses are also used in the auto-balance device in white. The APCG and Station Identification (SOS) signals are converted into digital words (AFA, AFB - for APCG and IFI - for SOS) and transmitted to the control processor via a digital bus. The demodulated composite color video signal (PCTV) exits through the separation buffer stage through pin 6 of the microcircuit. The external bandpass filter PF (see Fig. 1) selects the difference frequency signal, which is sent through pin 1 to the sound channel. PTsTV, in which the audio signal is suppressed by an external notch filter MODE, passes through pin 13 of the microcircuit to the internal video signal switch. A more detailed structure of a switch with three outputs is shown in fig. 3.
In addition to the signal from the output of the radio channel, the switcher can receive additional external video signals (PCTV or Y and C signals for S-VHS mode). The operating mode of the switch is selected via the digital bus with INA bits. INB, INC. When processing a signal from a radio channel and external sources, the INA bit is equal to 0. In this case, the distribution of signals at the outputs corresponds to Table. 1.
With the combination INB=1, INC=0, the S-VHS mode is enabled. The Y signal from input 11 passes to the brightness channel, and the color component C from input 10 passes to the color channel to the color filters. At pin 38, the PCTV is formed by summing the S-VHS components. In channel Y PTTV. after passing the adjustable delay line of the LDL and the chrominance signal rejector, it enters the edge sharpener and the noise suppressor. The delay is adjusted in steps of 40 non-bit YDO-YD3. To isolate chrominance signals in the color channel, parallel-connected gyratory bandpass filters are used - wideband for PAL/NTSC signals and narrowband (NBF) for SECAM. An AGC device is included in front of the color filters with adjustment limits from +6 to -20 dB. If the TV is powered by an S-VHS VCR, then the color rejector is turned off, and a constant additional delay of 160 ns is added instead. Then the brightness signal passes through the edge sharpener regulated on the digital bus and the noise suppressor m exits through pin 28. From the input of the adjustable LZ, the brightness signal inside the microcircuit comes to the line synchro-lecturer. From the third output of the switch, the selected PCTV is fed through pin 38 of the microcircuit to an external separation comb filter (for example, to the SAA4961 microcircuit). The output signals from this filter, as shown in Fig. 1 are led to terminal 11 (for the Y component) and to terminal 10 (for the chrominance component). In this mode, the INA bit is 1. and the switch mode is defined in Table 2. XNUMX. Moreover, both internal and external PCTV can be processed in the comb filter.
The color signals from the outputs of the bandpass filters are fed inside the microcircuit to a color decoder, a detailed block diagram of which is shown in Fig. 4. It uses separate PAL/NTSC and SECAM demodulators. The reference color subcarrier for PAL/NTSC demodulators is generated by the PLL, which is turned on for the duration of the color bursts. It contains the GUN. the frequency of which is set by one of two external quartz resonators connected to pins 34 and 35 of the microcircuit, an external low-pass filter connected to pin 36. a PD phase detector that compares the phase of the flash with the phase of the orthogonal component of the VCO output signal, as well as a phase shifter (PV), through which the color tone is adjusted in NTSC mode (controlled via the digital bus by HUEO - HUE5 bits). The error signal generated by the phase detector is proportional to the Sin(2pΔft) function. where Δf = fryн-fоcn.
An exemplary VCO signal with a phase of 0° (H0) acts on the signal demodulator U. An orthogonal exemplary signal with a phase of 90° (H90) passes to the demodulator of the V signal through a phase inverter controlled by half-line frequency pulses. The reference signal with phase 0° (F^) inside the microcircuit is used to calibrate the gyratory filters and the horizontal pulse generator, and also goes outside through pin 33 to control the comb filter. The SECAM demodulator is designed as a PLL. The VCO in it is calibrated with a frequency (4,43 MHz) of a quartz resonator connected to pin 35. The reference voltage is stored by a capacitor connected to pin 16. The demodulated signal passes through a gyratory CNR and a switch controlled by half-line frequency pulses, which distributes the components RY and BY in two channels per line. The signals RY and BY from the parallel outputs of the demodulators are fed to two gyratory delay lines for the line time, which suppress differential-phase distortions in the PAL mode and make up for the missing information in the SECAM mode. The signals from the outputs of the delay lines go through pins 29 and 30. In addition, the decoding unit contains an automatic recognizer of the received color standard, which is controlled via a digital bus, switches the internal circuits of demodulators (PS signal), and generates pulses of half-line frequency H/2. Bits XA, XB. coming to the recognizer indicate which quartz resonators are connected to pins 34 and 35. The Y, U / (BY) and V / (RY) signals output from the microcircuit through pins 28 - 30 can either undergo additional processing (reducing the duration of color transitions with the TDA4565 microcircuit, optimizing the Y-characteristics with the TDA9170 microcircuit or improving the transient response of the Y channel with the TDA9178 microcircuit) , or without processing, come to the microcircuit through pins 27, 31, 32. In the TDA8842 microcircuit, the possibility of additional external processing of the Y, U, V signals is not provided. Entered back into the microcircuit through pins 31. 32 U / (BY) signals. V/(RY) undergo (Fig. 5) fixing black levels, dynamic skin color correction and saturation adjustment. In a separate matrix, a GY signal is formed from them, and Dee they go to the R, G, B matrix, to which the brightness signal enters the microcircuit through pin 27 and passes the amplitude characteristic corrector in the region of low brightness. The skin color corrector is enabled by the DS bit. The DSA bit is used for control. When it is 0, the skin color vector has an angle of 117°. With DSA. equal to 1. the angle increases to 123°. which gives the image a colder tone preferred by American users.
The microcircuit uses an M matrix switchable via a digital bus, which has two modes of operation: standard PAL matrix (EBU) and matrix corresponding to the characteristics of Japanese kinescopes. Control is provided by the MAT bit. After the matrix, a fast electronic switch is included, which allows you to enter external text signals (R, G, B)1 instead of internal ones (for example, teletext signals). The switch is controlled through pin 26 and via bus IX. If the output DC voltage is less than 3V and IE1 is 0, the internal signals R.G, B are used. If IE1 is 1, the external signals R, G.B are output. voltage at pin 1, more than 1 V. the kinescope receives indication signals from the control processor. These signals come to conclusions 26-4. After the switch, the RG B signals pass (Fig. 6) to the contrast and brightness controls controlled via the digital bus, as well as the blue color correction cascade. The latter is enabled by the BLS bit. It reduces the amplitudes of the R and G components by 14% when the signal swing exceeds 80%. This brightens the white areas of the image. The EBS bit further increases the blue correction (the R signal is reduced by 20% and the G signal by 8%).
The TDA8854 chip provides the ability to process the second group of external signals (R, G, B) 2 and control the IE2 bit. These signals first pass through a matrix that converts them into Y, U, V signals. The latter go to an electronic switch, the outputs of which are connected to pins 28 - 30 of the microcircuit, and the internal signals Y, U, V from the outputs of the brightness channel and lines are connected to the second inputs. delay per line. The control signal applied to output 44 selects a group of signals for further processing. There is no such switch and matrix in the TDA8844 chip, and internal signals always come to pins 28 - 30. In this case, only the first group of external signals (R, G, B) is used, which pass to the second inputs of the fast switch connected at the output of the matrix R, G, B. Automatic white balance adjustment is provided by changing the gain of the channels at two points: in the region of dark currents (the current through the feedback pin 18 is approximately 8 μA) and in white (the current through the feedback pin 18 increases to 20 μA). Adjustment takes place alternately in adjacent fields. In each mode, three measuring pulses are applied, which are formed in a special device and are introduced into the R, G, B signals. WPR bits. WPG and WPB (six values each) adjust the swings of the signals in white. The leakage current is measured in each field. After turning on the TV, the auto-balance device is blocked for the duration of the kinescope warm-up (BCF bit). Signals for limiting the currents of the rays and protecting the kinescope pass to pin 22 of the microcircuit (in case of malfunctions of the frame scanning nodes). The limitation occurs on the average and peak current by adjusting the contrast and brightness. Frame protection blocks the output signals R. G, B, if the mode of the frame chip is violated. To do this, the TDA835x series microcircuits, usually used in the block, generate special pulses at their pin 8, which are sent to the pin 22 of the TDA884X video processors After fixing the black levels and drivers, the signals R. G, B leave the microcircuit through pins 19-21 and come to the kinescope cathodes through external video amplifiers. The amplitude of the signals on the cathodes of the kinescope is regulated by bits CL0 - CL2 from 57 to 107 V. The PTsTV from the input of the adjustable LZ luminance signal (see Fig. 3) in the switching and filter unit passes into the horizontal sync selector (Fig. 7). The device that generates horizontal trigger pulses contains two PLL systems. The first of them is controlled by the received video signal, the second - by line-scan retrace pulses. The VCO frequency is calibrated by the color subcarrier signal Fsc of the decoder. Calibration takes place in the blanking interval over the fields. The video signal is synchronized with the VCO signal by a coincidence detector that highlights the SL bit. The detector sensitivity can be reduced by 5 dB, which eliminates the reception of weak signals. The time constant of the first PLL is changed by the FOA bits. FOB. These bits are equal to 0 when the unit is operating from the air. When using an external DTV (for example, from a VCR), FOA and FOB are equal to 1.
The second PLL stabilizes the position of the image on the screen. The phase of the signal is controlled by the HSH bits (A0-A5). A multi-link protection system for the horizontal output transistor is provided, which turns on the channel only if all the conditions necessary for its normal operation are met. The triggering horizontal pulses exit the microcircuit through pin 40 (an open collector transistor). In steady state, the output is level 1 for 45% of the sweep period. Pin 41 receives horizontal feedback pulses. Three-level SSC signals are formed on the same pin. To obtain personnel triggering pulses, a controlled line frequency divider is used. The sawtooth signal is formed at pin 51 (Fig. 8) by an external capacitor. The TDA8844 chip is designed to use a symmetrical vertical scan output stage (for example, on the TDA8356 chip), which is controlled by two signals of different polarity taken from pins 46 and 47 of the video processor. These signals pass through the preliminary nodes for correcting the geometry of the raster vertically. The VA bits change the signal amplitude, the VSH bits shift the raster vertically, the SC bits provide S-correction, the VX - ZOOM mode, and the VSC bits change the vertical linearity (all of these bits have six values).
In addition, for a TV set with a kinescope having a deflection angle of 110 °, a signal is generated that provides horizontal screen correction (East-West correction - 0W also has six values). It is removed from pin 45 of the microcircuit and fed to a special modulator in the line scan unit, where it corrects the amplitude of the scan signal depending on the vertical displacement of the beams. Pin 50 is used to supply a signal to protect the TV from overvoltage on the second anode of the kinescope (XPR bit). In addition, the influence of the currents of the kinescope rays on the image size is excluded. The difference frequency radio signal after the external band-pass filter comes to the sound channel of the microcircuit through pin 1 (Fig. 9). In it, the signal is processed by an internal band-pass filter (1 ... 10 MHz), which provides noise reduction, an amplitude limiter, and is demodulated by a frequency detector with a PLL. The PLL capture bandwidth is 4.2...6,8 MHz, which ensures the processing of signals of all standards. After the low-pass filter, the audio signal passes a switch (mute) controlled by a digital bus (SM bit) and a frequency equalizer. The external corrector capacitor is connected to terminal 55. which is connected to the SCART connector. With a deviation equal to 50 kHz. an audio signal with an amplitude of 500 mV is emitted.
A bus-switched ATI attenuator feeds the internal audio signal to the switcher, allowing an external signal to be input instead. Then the circuit of automatic volume stabilization (ARUZ) and its operational regulator, controlled via a digital bus, are turned on. The adjustment can be turned off, and then the output (pin 15) receives a sound signal with a constant amplitude indicated above, with the same deviation. Let us briefly consider the control system of the TDA8844 chip through a digital bidirectional two-wire 1gC bus. In table. 3 shows the contents of the internal registers into which information is written via the bus. In total, the microcircuit contains 27 registers filled with information from the central processor, and three status registers, information from which is read into the control processor. In write mode, the chip has the address 10001010 (138 in decimal). In read mode, the address is incremented by one. Each register has a sub-address (in hexadecimal form).
Register 00 contains the previously discussed bits INA, INB, INC. controlling the video signal switcher, and bits FOA, FOB, changing the time constant of the PLL in the horizontal scanning channel. The BSO bit controls the auto white balance device. When it is 0, an internal delay is introduced into the ABB circuit. The XA, XB bits mentioned earlier provide information about which quartz resonators are connected. When both bits are at level 34, quartz resonators with a frequency of 35 MHz are connected to pins 3,58 and 01. With a combination of bits 34, respectively, a 3,58 MHz resonator is connected to pin 35, and pin 10 is free. With a combination of 4,43, a 35 MHz resonator is connected only to pin 11. Finally, a set of bits of 3,58 corresponds to a 34 MHz resonator connected to pin 4,43 and a 35 MHz resonator to pin XNUMX. The latter mode corresponds to a PAL / NTSC / SECAM TV . In register 01, the FORF and FORS bits control the frame rate: a combination of 00 automatically sets the frequency to 60 Hz if the PLL is not closed; in the case of levels 01, the frequency will be forced to 60 Hz; with values of 10, the frequency corresponding to the received signal is automatically set; finally, when the levels are 11 and the PLL loop is not closed, the frequency is set to 50 Hz. The DL bit controls interlacing, which is enabled when DL is 0. The STB bit causes the machine to transition from standby to operational when STB is 1. The POC bit enables (level 0) or disables (level 1) horizontal sync. Bits CM0-CM2 determine the color channel mode in accordance with Table. 4.
Register 02 (Table 3) contains the HBL bit, which controls line blanking. If it is 0, blanking occurs only during the reverse sweep. When the bit is set to 1, the blanking also applies to the beginning and end of the forward stroke. This allows you to fit a 4:3 format frame into a 16:9 kinescope screen. The AKB bit enables the auto white balance device when the AKB is 0. The HUEO-HUE5 digital words provide NTSC color tone adjustment within the range of -40...+38.75°. In register 03, the VIM bit serves as an indicator of the input video signal type (internal or selected by the INA, INB INC bits). The GAI bit sets the luminance channel gain (high when GAI. is 1). The remaining digital words bit DO-D5 in register 03 and registers 04-14,16,17 are used to adjust the parameters of the raster, image and sound in accordance with the explanations in Table. 3. Register 08 also includes the NCIN bit, which allows you to adjust the mode of operation of the vertical frequency divider.' The STM bit changes the sensitivity of the Signal Identification System (SOC): when STM is set to 1, signals from weak stations are not recognized. In register 09, setting the value of the VID bit to 1 excludes the influence of the COS system on the horizontal PLL time constant. When the LBM bit is set to 0, the blanking is automatically adapted to the 50 or 60 Hz standard. When the LBM bit is set to 1, forced blanking occurs according to the 50 Hz standard. In the OA register, depending on the value of the HCO bit, when the high voltage changes, either only the vertical size of the raster is corrected, or, moreover, when the HCO is equal to 1, the value of the EW signal changes. The EVG bit is used to protect the machine when vertical scanning is disabled. In this case, either the NDR status bit only changes, or the R, G channels are also turned off. The OB register contains the SBL bit, which enables (at level 1) overhead blanking. In this case, the lower half of the raster is extinguished. The PRO bit provides surge protection. If it is equal to 1, horizontal scanning is blocked during overvoltage (voltage at pin 50 exceeds 3,9 V). The OE register includes the MAT bit. providing switching matrix R, G, B. When it is equal to 1, the PAL matrix is used, and when it is 0, the NTSC matrix (in the Japanese version) is obtained. In register 10, the RBL bit provides blanking of the R, G, B output signals when RBL is 1. The COR bit, when set to 1, turns on the denoiser in the detail corrector. Register 11 contains the IE1 bit. When it is equal to 1, the normal operation of the FB (fast blank) pulses for external signals (R, G, B)1 is ensured. The IE2 bit turns on the second group of external inputs (R, G. B) 2 (for the TDA8854 chip). In register 12, when the value of the AFW bit changes from level 0 to level 1, the acquisition bandwidth of the AFCG system is expanded from CO to 275 kHz. Decreasing the value of the previously mentioned IFS bit from 1 to 0 lowers the gain of the UPGA by 20 dB. Register 13 includes the previously mentioned MOD bit. Increasing its value to 1 puts the channel into positive modulation mode (to receive the French L standard). When the value of the VSW bit increases to 1, suppression of the video signal coming from the radio channel is provided. As a result, an external video signal can be applied to input 17. Register 14 contains the SM bit, which is used to turn off the sound when the bit is 1. Changing the value of the FAV bit from 0 to 1 changes the volume from the nominal value to a fixed value with an attenuation of 0 dB. Register 15 contains the previously mentioned IFA bits. IFB, IFC allow you to select the value of the intermediate frequency. It is equal to 38 MHz when the bit values are 011 respectively. The 010 bit set raises the intermediate frequency to 38,9 MHz, which is used in Western Europe. In register 18, if the OSO bit is set to 1, vertical scanning is turned off when the vertical size of the raster is exceeded. The VSD bit, when set to 0, enables vertical scanning. The CB bit changes the center frequency of the chrominance channel. Increasing the bit to 1 increases it by a factor of 1,1. Increasing the BIS bit to 1 turns on blue correction for large video swings. When the BKS bit is set to 1, amplitude response correction is provided in dark areas of the image. Bits CSO, CS1 switch the output of PCTV2 in the TDA8854 chip. When the BB bit is 1, a blue raster is obtained when there is no signal. Register 19 contains the NEW bit. If it is equal to 1, the helper is blanked when a PAL-plus signal is received. BPS bit. equal to 1 results in blocking the delay lines in the chrominance block. When the ACL bit is set to 1, chrominance clipping is enabled. When the CMB bit is 1, a comb filter can be connected to the chip. The PTsV is fed to the filter input from pin 38, and the separated luminance and chrominance signals pass to the S-VHS inputs (pins 11 and 10) of the microcircuit. The AST bit controls how the TV turns on. With its level equal to 0, the inclusion occurs automatically, and at level 1 it is controlled by the microprocessor. The CLO-CL2 bits have been discussed before. In register 1A, the adjustment of the YDO-YD3, DS and DSA bits has been said before. Increasing the mentioned FFI bit to 1 reduces the PLL time constant in the UPCH. The EBS bit provides in it an additional stretching of the amplitude characteristic for the "blue" signal. Status register 00 contains the ROY bit. When it is 1. the TV goes into standby mode. Bit FS1 indicates synchronous vertical scanning: at level 1 - at a frequency of 60 Hz; at level 0 - at a frequency of 50 Hz. When the SL bit is set to 1, the first horizontal PLL loop is closed. BhtXPPi is equal to 1 when the voltage at pin 50 of the video processor exceeds 3,9 V. This indicates the possibility of X-ray emission. Bits CD0-CD2 provide an indication of the received color standard. In status register 01 at NDF bit. equal to 1, vertical scanning is disabled. When the IN1 bit is 0, the FB1 pulses on pin 26 are active. IFI bit. equal to 1. means the recognition of the received signal. AFA bits. AFB indicate the mode of operation of the APCG system So, bit AFB. equal to 0 corresponds to an increase in frequency, and its level 1 means a decrease in frequency. Bits SXA, SXB signal the inclusion of quartz resonators in accordance with Table. 5.
In status register 02, if the BCF bit is 1, it means that the ABB loop is not closed. Additional bit N2 is equal to 1. The IVW bit indicates the parameters of the frame divider. Bit IVW. equal to 1 means standard video signal 525/625 lines, IVW bit equal to 0 indicates that. that the standard video signal is not detected. The IDO-ID3 bits report the type of microcircuit used in accordance with Table. 6.
To turn on the TDA8844 video processor, you must perform the following operations:
For horizontal scanning to work, all subaddress bits must be loaded. Registers that are not used are loaded with a value of 0. A simplified schematic diagram of turning on the TDA8844 video processor is shown in fig. 10. The device uses a channel selector with frequency synthesis SK1101 from the Finnish company SALORA. The ZQ5 SAW filter provides D/K and B/G signal processing. The demodulated LCTV from pin 6 of the DA1 video processor is fed to the emitter follower on the VT1 transistor. Ceramic band pass filters ZQ1 and ZQ2 are connected in accordance with the accepted television standard. The selected signal of the difference audio frequency passes to output 1 of the video processor.
The emitter circuit of the transistor VT1 also includes ceramic sound notch filters ZQ3, ZQ4. Through the emitter follower on the transistor VT2, the notched video signal comes to pin 13 of the DA1 chip. The module is designed for signal processing systems SECAM, PAL and NTSC-4.43. Therefore, only one 6 MHz ZQ4,43 crystal was used, connected to pin 35. The demodulated audio signal from pin 15 is input to mono amplifier 34 on the DA3 chip. An external sound signal can be applied to pin 2 of the DA1 chip. An external PCTV is fed to output 17 of the video processor. The demodulated signals YU, V go to connector XII. They can be subjected to external processing or returned to the microcircuit through the jumpers shown in the diagram. The demodulated PTTV goes to the X10 connector, which is used to connect the comb filter. The diagram shows the connection of the DA2 chip of the vertical sweep output amplifier. For simplicity, the connection of pin 8 of this microcircuit with pin 22 of the video processor (protection against turning off the frame scan), as well as the current limiting circuit of the kinescope beams, is not shown. Output frame signals go to connector X8. To control the TDA8844 video processor, Philips releases the SAA5296 processor with a version of the CTV832S program (or R with a Russian-language menu). Author: B.Khokhlov, Moscow
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