|
Arabic
Bengali
Chinese
English
French
German
Hebrew
Hindi
Italian
Japanese
Korean
Malay
Polish
Portuguese
Spanish
Turkish
Ukrainian
Vietnamese|
ENCYCLOPEDIA OF RADIO ELECTRONICS AND ELECTRICAL ENGINEERING USB bus and FireWire. Encyclopedia of radio electronics and electrical engineering
Encyclopedia of radio electronics and electrical engineering / Computers USB (Universal Serial Bus - Universal Serial Bus) is an industry standard extension of the PC architecture, focused on integration with telephony and consumer electronics devices. Version 1.0 was published in January 1996. The USB architecture is defined by the following criteria:
From the end user's point of view, the following features of USB are attractive:
Since mid-1996, PCs have been produced with a built-in USB controller implemented by the chipset. Modems, keyboards, scanners, speakers and other USB-enabled input/output devices are expected to appear, as well as monitors with USB adapters, they will play the role of hubs for connecting other devices. 1.1. USB structure USB allows simultaneous data exchange between host computer and many peripheral devices (PU). The distribution of bus bandwidth between PUs is planned by the host and implemented by it by sending tokens. The bus allows you to connect, configure, use and disconnect devices while the host and the devices themselves are running. The following is an author's translation of terms from the "Universal Serial Bus Specification. Revision IOJanuary 15, 1996" published by Compaq, DEC, IBM, Intel, Microsoft, NEC, and Northern Telecom. More detailed and up-to-date information can be found at usb.org. Devices USBs can be hubs, functions, or a combination of both. Hub (Hub) provides additional connection points for devices on the bus. Functions USB provides additional features to the system, such as ISDN connection, digital joystick, digital interface speakers, etc. The USB device must have a USB interface that fully supports the USB protocol, performs standard operations (configuration and reset), and provides information describing device. Many devices connected to USB have both a hub and functions. The operation of the entire USB system is controlled by host controller (Host Controller), which is the hardware and software subsystem of the host computer. Physical connection devices is carried out according to the topology of a multi-tiered stars. The center of each star is hub, each cable segment connects two hub points to another hub or function. The system has one (and only one) host controller, located at the top of the pyramid of devices and hubs. Host controller integrates with root hub (Root Hub), providing one or more connection points ports. The USB controller included in the chipsets usually has a built-in two-port hub. Logically, a device connected to any USB hub and configured (see below) can be considered as being directly connected to the host controller. Functions are devices capable of transmitting or receiving data or control information over the bus. Typically, the functions are separate PUs with a cable connected to the hub port. Physically, in one case there can be several functions with a built-in hub that provides their connection to one port. These combo host devices are hubs with permanently connected function devices. Each function provides configuration information describing the PU's capabilities and resource requirements. The function must be configured by the host before it can be used, it must be allocated a channel bandwidth and configuration options selected. Examples of functions are: Pointers mouse, tablet, light pen. Input devices keyboard or scanner. Output device printer, speakers (digital). ISDN telephone adapter Hub a key element of the RnP system in the USB architecture. The hub is a cable hub. Connection points are called ports hub. Each hub transforms one connection point into many. The architecture allows connection of several hubs. Each hub has one upstream port designed to connect to a top-level host or hub. The rest of the ports are downstream (Downstream Ports), designed to connect lower-level functions or hubs. The hub can recognize the connection of devices to the ports or disconnection from them and manage the power supply to their segments. Each port can be enabled or disabled and configured for full or limited baud rates. The hub provides isolation of low-speed segments from high-speed ones. Hubs can control the power supply to downstream ports; provides for setting a limit on the current consumed by each port.
USB system is divided into three levels with certain rules of interaction. The USB device contains an interface part, a device part and a functional part. The host is also divided into three parts: interface, system and device software. Each part is responsible only for a certain range of tasks, the logical and real interaction between them is illustrated in Fig. 7.1. The structure under consideration includes the following elements: Physical USB device a device on the bus that performs functions of interest to the end user. Client SW Device-specific software running on a host computer. May be an integral part of the OS or a special product. USB System SW USB system support independent of specific devices and client software. USB host controller hardware and software for connecting USB devices to the host computer. Physical interface The USB standard defines the electrical and mechanical specifications for the bus. Information signals and a 5 V supply voltage are transmitted via a four-wire cable. The differential method for transmitting D+ and D signals over two wires is used. Static transmitter signal levels should be below 0,3V (low) or above 2,8V (high). Receivers withstand input voltage within 0,5...+3,8 V. Transmitters must be able to switch to a high-impedance state for bidirectional half-duplex transmission over a single pair of wires. Two-wire transmission in USB is not limited to differential signals. In addition to the differential receiver, each device has D+ and D- line receivers, and the transmitters of these lines are controlled individually. This makes it possible to distinguish between more than two line states used to organize a hardware interface. states DiffO и diff1 are determined by the potential difference on the lines D + and D more than 200 mV, provided that on one of them the potential is above the VSE threshold. The condition in which both inputs D+ and D are low is called linear zero (SEO Single-Ended Zero). The interface defines the following states: DataJ State и Data To State state of the transmitted bit (or simply J и TO), defined via states DiffO и Diff1. idle state bus pause. Summary State wake-up signal to wake the device from sleep mode. Start of Packet (SOP) start of packet (jump from Idle State in K). End of Packet (EOP) end of package. Disconnect the device is disconnected from the port. Connect the device is connected to the port. Reset device reset. States are determined by combinations of differential and linear signals; for full and low speed condition DiffO и diff1 have the opposite purpose. In state decoding Disconnect, Connect и Reset the time spent by lines (more than 2,5 ms) in certain states is taken into account. The bus has two transmission modes. full speed USB signaling is 12 Mbps, low 1,5 Mbps. For full speed, shielded twisted pair with an impedance of 90 ohms and a segment length of up to 5 m is used, for low - unshielded unshielded cable up to 3 m. Low-speed cables and devices are cheaper than high-speed ones. The same system can use both modes at the same time; switching for devices is transparent. The low speed is designed to work with a small number of launchers that do not require high speed. The speed used by the device connected to a particular port is determined by the hub by the levels of signals on the D+ and D- lines, biased by the terminating resistors R2 of the transceivers (see Figures 7.2 and 7.3). Synchronization signals are encoded along with data using the method NRZI (Non Return to Zero Invert), his work is illustrated in Fig. 7.4. Each packet is preceded by a sync field synch, allowing the receiver to tune in to the transmitter frequency. The cable also has VBus and GND lines to carry the 5V power supply to the devices. The cross section of the conductors is selected in accordance with the length of the segment to ensure a guaranteed signal level and supply voltage.
The standard defines two types of connectors (See Table 7.1 and Figure 7.5).
Type "A" connectors used to connect to hubs (Upstream connector). Plugs are installed on cables that are not disconnected from devices (for example, keyboard, mouse, etc.). Nests are installed on downstream ports (Downstream Port) hubs. Connectors type "B" (Downstream Connector) installed on devices from which the connection cable can be detached (printers and scanners). The mating part (plug) is installed on the connecting cable, the opposite end of which has a type "A" plug. Types "A" and "B" connectors differ mechanically (Fig. 7.5), which eliminates invalid loop connections of hub ports. The four-pin connectors are keyed to prevent misconnection. The design of the connectors provides late connection and early disconnection of signal circuits compared to supply circuits. To recognize the USB connector, a standard symbolic designation is placed on the device case.
Device power USB possible from cable (Bus-Powered Devices) or from your own power supply (Self-Powered Devices). The host provides power to the PUs directly connected to it. Each hub, in turn, provides power to devices connected to its downstream ports. With some topology restrictions, the use of bus-powered hubs is allowed. On fig. 7.6 shows an example of a USB device connection diagram. Here, the keyboard, pen, and mouse can be bus-powered.
Data transfer model Each USB device is a set of independent endpoints (Endpoint), s which the host controller exchanges information. Endpoints are described by the following parameters: the required frequency of bus access and allowable service delays; required channel bandwidth; point number; error handling requirements; maximum sizes of transmitted and received packets; exchange type; exchange direction (for continuous and isochronous exchanges). Each device necessarily has an endpoint numbered 0, used for initialization, general control and polling of its status. This point is always configured when the device is powered on and connected to the bus. It supports "control" transfers (see below). In addition to the zero point, function devices may have additional points that implement a useful data exchange. Low speed devices can have up to two additional points, full speed devices up to 16 input points and 16 output points (protocol limitation). Points cannot be used until they have been configured (a channel matched to them has been established). Channel {Pipe) USB refers to the data transfer model between host controller and endpoint (End point) devices. There are two types of channels: streams (Stream) and messages (Message). Flow delivers data from one end of the channel to the other, it is always unidirectional. The same endpoint number can be used for two input and output stream channels. A thread can implement the following exchange types: continuous, isochronous, and interrupts. Delivery is always in first-in-first-out (FIFO) order; from the USB point of view, stream data is unstructured. Messages are in the format defined by the USB specification. The host sends a request to the endpoint, after which a message packet is transmitted (received), followed by a packet with endpoint state information. A subsequent message normally cannot be sent until the previous one has been processed, but unhandled messages may be discarded during error handling. Two-way messaging is addressed to the same endpoint. For the delivery of messages, only an exchange of type "control" is used. Channels have characteristics associated with the endpoint (bandwidth, type of service, buffer size, etc.). Channels are established when configuring USB devices. There is a message channel for each enabled device (Control Pipe 0) through which configuration, control, and status information is transmitted. Data transfer types USB supports both unidirectional and bidirectional communication modes. Data is transferred between the host software and the endpoint of the device. The device can have several endpoints, communication with each of them (channel) is established independently. The USB architecture allows four basic types of data transfer: Control Transfers, used for configuration during connection and during operation to control devices. The protocol provides guaranteed data delivery. The length of the data field of the control message does not exceed 64 bytes at full speed and 8 bytes at low. Bulk Data Transfers relatively large packages without strict delivery time requirements. Transmissions occupy the entire free bandwidth of the bus. Packets have a data field of 8, 16, 32, or 64 bytes. These transfers have the lowest priority and may be suspended if the bus is heavily loaded. Only allowed at full baud rate. Interrupts short (up to 64 bytes at full speed, up to 8 bytes at low speed) transfers such as input characters or coordinates. Interrupts are spontaneous and must be serviced no slower than the device requires. The service time limit is set in the range of 1-255ms for full speed and 10-255ms for low. Isochronous Transfers continuous real-time transmissions occupying a pre-negotiated portion of the bus bandwidth and having a given delivery delay. If an error is detected, isochronous data is transmitted without retry, invalid packets are ignored. An example is digital voice transmission. Bandwidth is determined by the requirements for transmission quality, and delivery delay can be critical, for example, when implementing teleconferencing. The bus bandwidth is shared among all installed channels. The allocated bandwidth is assigned to the channel, and if the establishment of a new channel requires a bandwidth that does not fit into an already existing allocation, the channel allocation request is rejected. The US B architecture provides for internal buffering of all devices, and the more bandwidth a device requires, the larger its buffer should be. USB must be able to transfer at such a speed that the data delay in the device caused by buffering does not exceed a few milliseconds. Isochronous transfers are classified according to the way the endpoints of sources or recipients of data are synchronized with the system: there are asynchronous, synchronous and adaptive device classes, each of which has its own type of USB channel. Protocol All exchanges (transactions) via USB consist of three packages. Each transaction scheduled and initiated by the controller, which sends token packet {Token Packet). It describes the transfer type and direction, the USB device address, and the endpoint number. In each transaction, only the exchange between the addressed device (its endpoint) and the host is possible. The device addressed by the token recognizes its address and prepares for the exchange. The data source (identified by the token) transmits a data packet (or notification that there is no data to transmit). After successfully receiving the packet, the data receiver sends acknowledgment packet (Handshake Packet). Transaction scheduling provides flow channel management. At the hardware level, the use of transaction abandonment (NAck) prevents buffers from overflowing from above and below if the transmission rate is invalid. Abandoned transaction tokens are retransmitted at bus time. Flow control allows flexible scheduling of services for simultaneous heterogeneous data flows. Error tolerance provide the following USB features: High signal quality achieved with differential receivers/transmitters and shielded cables. Protection of control fields and data with CRC codes. Device connection and disconnection detection and resource configuration at the system level. Self-healing protocol with timeout on packet loss. Flow control for isochronism and hardware buffer management. Independence of functions from unsuccessful exchanges with other functions. To detect transmission errors, each packet has CRC check fields to detect all single and double bit errors. The hardware detects transmission errors and the controller automatically tries the transmission three times. If the retries are unsuccessful, an error message is passed to the client software. Package formats Bytes are transferred over the bus sequentially, least significant bit first. All parcels are organized into packages. Each packet begins with a Sync field, which is represented by a sequence of states KJKJKJKK (NRZI encoded) following the state idle. Last two bits (QC) are the SOP packet start marker used to identify the first bit of the packet ID PIDs. The packet ID is a 4-bit field PID[3:0], identifying the type of packet (Table 7.2), followed by the same 4 bits as control bits, but inverted.
In marker bags IN, SETUP и OUT the following are address fields: 7-bit function address and 4-bit endpoint address. They allow addressing up to 127 USB functions (address zero is used for configuration) and 16 endpoints per function. The SOF packet has an 11-bit frame number field (Frame Number Field), sequentially (cyclically) increased for the next frame. Data field can be from 0 to 1023 integer bytes. The size of the field depends on the type of transmission and is negotiated when the channel is established. Field sks-cola present in all tokens and data packets, it protects all fields in the packet except PIDs. CRCs for markers (5 bits) and data (11 bits) are calculated using different formulas. Each transaction is initiated by the host controller by sending a token and ends with a handshake packet. The sequence of packets in transactions is illustrated in Fig. 7.7. The host controller organizes exchanges with devices according to its resource allocation plan. The controller cyclically (with a period of 1 ms) generates frames (Frames), which include all scheduled transactions. Each frame starts with a SOF token. (start of frame) which is the clock signal for all devices, including hubs. At the end of each frame, a time interval is allocated EOF (End Of Frame) during which the hubs prohibit transmission towards the controller. Each frame has its own number. The host controller operates on a 32-bit counter, but only transmits the lower 11 bits in the SOF token. The frame number is incremented (cyclically) during EOF. The host schedules the loading of frames so that they always have room for control and interrupt transactions. Free frame time can be filled with solid transmissions (Bulk Transfers).
For isochronous transmission Synchronization between devices and controller is important. There are three options: synchronization of the device's internal generator with SOF markers; adjusting the frame rate to the frequency of the device; matching the transmission (reception) rate of the device with the frame rate. Adjusting the frame rate of the controller is possible, of course, under the frequency of the internal synchronization of only one device. Adjustment is carried out through a feedback mechanism, which allows you to change the period of the frame within ±1 bit interval. 1.2. System configuration USB supports dynamic connection and disconnection of devices. Bus device numbering is an ongoing process that keeps track of changes in the physical topology. All devices are connected via hub ports. Hubs detect the connection and disconnection of devices to their ports and report the state of the ports when requested from the controller. The host enables the port and addresses the device through the control channel using Zero USB Default Address. During the initial connection or after a reset, all devices are addressed that way. The host determines whether the newly connected device is a hub or a feature and assigns it unique address USB. Host creates control channel (Control Pipe) with this device using the assigned address and destination number zero. If the new device is a hub, the host determines the devices connected to it, assigns addresses to them, and sets pours channels. If the new device is a feature, the connection notification is passed by the USB manager to the software concerned. When a device is disconnected, the hub automatically disables the corresponding port and reports the disconnection to the controller, which removes information about this device from all data structures. If the hub is disabled, the removal process is performed for all devices connected to it. If a feature is disabled, a notification is sent to the software concerned. device numbering, connected to the bus (Bus enumeration), performed dynamically as they are connected (or powered up) without any user or client software intervention. The numbering procedure is as follows: 1. The hub to which the device has connected informs the host about the change in the state of its port by responding to a status poll. From this point on, the device enters the state Attached (connected), and the port to which it connected to the state disabled. 2. The host checks the status of the port. 3. Having learned the port to which the new device is connected, the host issues a command to reset and enable the port. 4. The hub generates a Reset signal for this port (10 ms) and puts it into the state enabled. The connected device can draw up to 100 mA from the bus. The device enters the state Powered (power on), all its registers are reset, and it responds to address zero. 5. Until the device receives a unique address, it is available on the watchdog channel, through which the host controller determines the maximum allowable size of the data field of the packet. 6. The host tells the device its unique address, and it is put into the state addressed (addressed to). 7. The host reads the configuration of the device, including the declared current draw from the bus. Reading may take several frames. 8. Based on the information received, the host configures all available endpoints of this device, which is transferred to the state configured (configured). Now the hub allows the device to consume the full current declared in the configuration from the bus. The device is ready. When a device is disconnected from the bus, the hub notifies the host and the port is disabled and the host updates its current topology information. 1.3. USB devices features and hubs USB bus capabilities allow you to use it to connect a variety of devices. Without touching on the "useful" properties of the PU, let's focus on their interface part associated with the USB bus. All devices must support a set of common operations listed below. Dynamic connection and disconnection. These events are monitored by the hub, which reports them to the host controller and resets the connected device. The device after the reset signal must respond to the zero address, while it is not configured and not suspended. Once assigned an address that the host controller is responsible for, the device should only respond to its unique address. Configuration devices performed by the host is necessary for their use. For configuration, information read from the device itself is usually used. A device can have multiple interfaces, each with its own endpoint representing a function of the device to the host. An interface in a configuration may have alternative sets of characteristics; changing sets is supported by the protocol. To support adaptive drivers, device and interface descriptors have class, subclass, and protocol fields. Data transfer possible through one of four types of transfers (see above). For endpoints that allow different types of transfers, only one of them is available after configuration. Energy management is a highly developed feature of USB. For bus-powered devices, the power is limited. Any device connected must not draw more than 100 mA from the bus. The operating current (not more than 500 mA) is declared in the configuration, and if the hub cannot provide the declared current to the device, it is not configured and therefore cannot be used. The USB device must support suspension (Suspended Mode), in which its current consumption does not exceed 500 μA. The device should automatically suspend when bus activity ceases. Possibility Remote Wakeup allows a suspended device to signal a host that may also be in a suspended state. The remote wake capability is described in the device configuration. This feature may be disabled during configuration. Hub in USB, it performs signal switching and power supply, and also monitors the status of devices connected to it, notifying the host of changes. The hub consists of two parts of the controller (Hub Controller) and repeater (Hub Repeater). Repeater is a managed key that connects an output port to an input port. It has means to support resetting and suspending signaling. Controller contains registers for interacting with the host. Access to registers is carried out by specific commands for accessing the hub. The commands allow you to configure the hub, manage downstream ports and monitor their status. Downstream ports hubs can be in the following states: Powered (^(power off) no power is supplied to the port (only possible for hubs that switch nutrition). The output buffers are placed in a high impedance state and the input signals are ignored. Disconnected (disconnected) the port is not signaling in either direction, but is able to detect a connected device (by no state SEO within 2,5 µs). Then the port goes into the state disabled, and by the levels of input signals {DiffO or diff1 able idle) it determines the speed of the connected device. sDisabled (disabled) the port transmits only a reset signal (on command from the controller), signals from the port (except for disconnection detection) are not accepted. Upon detection of a trip (2,5 µs state SEO) port goes into state disconnect, and if a shutdown is detected by a "sleeping" hub, a signal will be sent to the controller Summary. w Enabled (Enabled) The port transmits signals in both directions. At the command of the controller or upon detection of a frame error, the port enters the state disabled, and upon detection of a trip to the state disconnect. Suspended (suspended) The port sends a signal to enter the stopped state ("sleep" mode). If the hub is in an active state, signals through the port are not passed in any direction. However, the "sleeping" hub perceives the state change signals of non-prohibited ports, giving "wake up" signals from the activated device even through the chain of "sleeping" hubs. The state of each port is identified by the hub controller using separate registers. There is a common register, the bits of which reflect the fact of a change in the state of each port (fixed during EOF). This allows the host controller to quickly find out the status of the hub, and if changes are detected by special transactions, update the status. 1.4. Host controller The host computer communicates with devices through the controller. The host has the following responsibilities: detection of connection and disconnection of USB devices; manipulation of the flow of control between devices and the host; data flow management; collection of statistics; ensuring energy saving by connected control units. The controller system software manages the interaction between devices and their software running on the host computer to negotiate: device numbering and configuration; isochronous data transfers; asynchronous data transfers; energy management; device and bus management information. Where possible, the USB software uses the host's existing system software, such as Advanced Power Management, for power management. 2. IEEE 1394-FireWire The High Performance Serial Bus standard, formally named IEEE 1394, was adopted in 1995. The goal was to create a bus that is not inferior to today's standard parallel buses, while significantly reducing the cost and improving the convenience of connection (due to the transition to a serial interface). Bus based standard firewire, used by Apple Computer as a cheap alternative to SCSI in Macintosh and PowerMac computers. The name FireWire is now applied to implementations of IEEE 1394 and coexists with the shorthand 1394. Benefits of FireWire before other serial buses: s? Multifunctionality: the bus provides digital communication for up to 63 devices without the use of additional equipment (hubs). Devices digital camcorders, scanners, printers, cameras for video conferencing, disk drives can exchange data not only with a PC, but also with each other. FireWire, initiated by VESA, is also positioned for "home networks". High bit rate and isochronous transfers allow even at the initial level (100 Mbps) to transmit simultaneously two channels of video (30 frames per second) of broadcast quality and a stereo audio signal with CD quality. s§ Low cost of components and cable. si Easy to install and use. FireWire extends the pnp system. Devices are automatically recognized and configured when powered on/off. Bus-powered (current up to 1,5 A) allows the remote control to communicate with the system even when their power is turned off. Not only PCs can control the bus and other devices, but also other "intelligent" devices, such as VCRs. 2.1. Structure and interaction of bus devices The 1394 standard defines two categories of busbars: cable busbars and crossover busbars. (Back plane). Under cross tires usually refers to parallel interfaces connecting the internal subsystems of a device connected to a 1394 cable. Unlike USB, which is controlled by a single host controller, the 1394 standard allows peer-to-peer devices to be connected on a network. A network may consist of multiple buses connected by bridges. Within the same bus, devices are connected by connecting cables without the use of additional devices. Bridges are special smart devices. The interface card for the FireWire bus for the PC is a PCI 1394 bridge. Addresses up to 63 devices on each bus, addressed by a 6-bit node ID field. The 10-bit bus identifier field allows up to 1023 bridges to be used in the system, connecting buses of different types. cable bus is a network consisting of nodes and cable bridges. Flexible topology allows you to build networks that combine tree and chain architectures (Fig. 7.9). Each node typically has three peer-to-peer connectors. Many device connection options are allowed with the following restrictions: ssi between any pair of nodes can be no more than 16 cable segments; the length of a standard cable segment should not exceed 4,5 m; 2nd total length of the cable should not exceed 72 m (the use of a better cable allows you to weaken this limitation). Some devices may only have one connector, limiting their location options. The standard allows up to 27 connectors on a single device.
The standard provides for the connection of nodes using a 6-wire cable enclosed in a common shield. Two twisted pairs are used for signal transmission (separate for the receiver and transmitter), two wires are used to power devices (8-40 V, up to 1,5 A). For galvanic isolation of the interface, transformers are used (isolation isolation voltage up to 500 V) or capacitors (in cheap devices with isolation voltage up to 60 V relative to the common wire). Fig. 7.10 gives an idea of the connectors. 700. Some devices (Sony DCRVX1000 and DCR-VX1000 camcorders, as well as DHR-4 DVCR) have only one smaller XNUMX-pin connector with signal circuits only. These devices are connected to the bus via a special adapter cable only as terminal devices (although special splitter adapters can be used). The 1394 standard defines three possible frequencies for signaling over cables: 98,304, 196,608, and 393,216 Mbps, which are rounded up to 100, 200, and 400 Mbps. The frequencies in the standard are designated as S100, S200 и S400 respectively. Consumer devices usually support S100, most adapters allow S200. Devices designed for different speeds can be connected to the same bus. The exchange will take place at the minimum speed for all active nodes. However, if the host controller implements a topology and speed map (Topology_Mar и Speed_Map), it is possible to use several frequencies in one bus, in accordance with the capabilities of a particular pair involved in the exchange. The system allows dynamic (hot) connection and disconnection of devices. Connectable identifiers devices are assigned automatically, without user intervention. Topology changes (composition of connected devices) are automatically tracked by the bus and transmitted to the control software. IEEE 1394 protocol Protocol 1394 is implemented at three levels (Figure 7.11). Transaction Layer converts packets to data provided to applications and vice versa. It implements a request-response protocol conforming to ISO/IEC 13213:1994 (ANSI/IEEE 1212, edition 1994), CSR (Control and Status Register) architectures for microcomputer buses (read, write, lock). This makes it easier to link the 1394 bus to standard parallel buses. Link Layer forms packets from physical layer data and performs inverse transformations. It provides the exchange of nodes with datagrams with acknowledgments. The layer is responsible for transmitting packets and managing isochronous transfers. Physical Layer generates and receives bus signals. It provides initialization and arbitration, assuming that only one transmitter is active at any given time. The layer passes the data streams and signal levels of the serial bus to the higher layer. Between these levels, galvanic isolation is possible, in which the physical layer microcircuits are powered from the bus. Galvanic isolation is necessary to prevent parasitic common wire loops that can appear through the protective earth wires of the power supplies. The FireWire hardware usually consists of two dedicated physical layer transceiver chips. PHY Transceiver and bus link bridge LINK Chip. Communication between them is possible, for example, via the IBM-Apple LINK-PHY interface. Communication layer microcircuits perform all the functions of their layer and some of the functions of the layer transactions, the rest of the transaction layer is done in software.
Connectors Fig. 7.11. Three-layer structure of FireWire Bus management The 1394 protocol has a flexible mechanism for managing communication between different devices. This does not require the presence of a PC or other bus controller on the bus. Management includes three services: cycle master, sending start-of-cycle broadcasts (required for isochronous exchanges). isochronous resource manager, if any node supports isochronous exchange (for digital video and audio). Optional bus controller (Bus Master) it can be a PC or an editing DVCR. On reset, the bus structure is determined, physical addresses are assigned to each node, and the loop master, isochronous resource manager, and bus controller are arbitrated. One second after the reset, all resources become available for later use. The principal advantage of the bus is that there is no need for a controller. Any transmitting device can receive a strip of isochronous traffic and start transmitting on an autonomous or remote control signal, the receiver will "hear" this information. In the presence of a controller (PC), the corresponding software can control the operation of devices, realizing, for example, a digital non-linear video editing studio. Isochronous data transport Isochronous bus transport 1394 provides guaranteed throughput and limited latency for high-speed transmission over multiple channels. The isochronous resource manager contains a register BANDWIDTH^AVAILABLE, which determines the availability of the remaining bandwidth for nodes with isochronous transmission. Upon reset, a newly appeared node with isochronous transmission requests a lane allocation. Digital video, for example, requires 30 Mbps of bandwidth (25 Mbps for video data and 3-4 Mbps for audio, sync, and packet headers). Bandwidth is measured in special allocation units, of which there are 125 in a 6144-millisecond cycle. A unit takes about 20 ns, which corresponds to the time required to transmit one quadlet (Quadlet) at 1600 Mbps. Quadlet (32-bit word) is the unit of data transfer on the bus. 25 ms of the cycle is reserved for asynchronous traffic, so the initial value of the register after the reset is 4915 units. IN S100 digital video devices request about 1800 units, in S200 about 900. If the corresponding band is not available, the requesting device will periodically repeat the request. The isochronous resource manager assigns each isochronous node a channel number (0-63) from among those available (register CHANNELS_AVAILABLE). It is the identifier of the isochronous package. When an isochronous exchange becomes unnecessary for a node, it must release its bandwidth and channel number. Control information is exchanged over an asynchronous channel. 2.2. Synonyms and extensions of the IEEE 1394 standard The IEEE 1394 bus has many aliases: IEEE 1394-1995 Standard for a High Performance Serial Bus is the full name of the document describing the standard currently in effect. FireWire is a trademark of an implementation of IEEE-1394 by Apple Computer, Inc. P1394 is the name of the preliminary version of IEEE-1394 (prior to adoption in December 1995). DigitalLink is a Sony Corporation trademark used in reference to the implementation of IEEE-1394 in digital cameras. MultiMedia Connection is the name used in the 1394 High Performance Serial Bus Trade Association (1394TA) logo. Since Apple has been developing the concept of FireWire since 1986, the name FireWire is the most common synonym for IEEE 1394. In addition to the main IEEE 1394-1995 standard, there are several modifications of it: The 1394a is considered a clean document, filling in some of the gaps in the original standard and having minor changes (such as a faster reset operation on the bus). 1394a products are backwards compatible with devices released before the adoption of the main standard. The version was introduced to increase the speed to 800 Mbps and higher, high-speed versions are also included in 1394b. 1394.1 defines the 4-wire connector and sets the standard for bus bridges. 1394.2 is intended as a standard for connecting a cluster of stations with an exchange rate of 1 Gb / s and higher, incompatible with 1394. This standard stems from the IEEE 1596 SCI (Scalable Coherent Interface) for supercomputers and is sometimes referred to as Serial Express or SCILite. The 1394.2 signaling interface is similar to FCAL and allows ring topology, prohibited by the 1394 standard. 2.3. Comparison of FireWire and USB FireWire and USB serial interfaces, while having common features, are essentially different technologies. Both buses allow easy connection of a large number of PUs (127 for USB and 63 for FireWire), allowing switching and turning devices on / off while the system is running. The topology of both buses is quite close. USB hubs are part of the CC; their presence is invisible to the user. Both buses have device power lines, but the power handling capacity for FireWire is much higher. Both buses support PnR (Power On/Off Auto Configuration) and eliminate the problem of address shortages, DMA channels, and interrupts. There is a difference in bandwidth and bus management. USB focused on PU connected to a PC. Its isochronous transmissions only allow digital audio signals to be transmitted. All transmissions are centrally controlled and the PC is the necessary control node at the root of the bus tree structure. The connection of several PCs with this bus is not intended. FireWire is focused on intensive exchange between any devices connected to it. Isochronous traffic allows you to transmit "live" video. The bus does not require centralized control from the PC. It is possible to use the bus to combine several PCs and PUs into a local network. New digital video and audio devices have built-in 1394 adapters. FireWire connection of traditional analog and digital devices (players, cameras, monitors) is possible through adapters-converters of interfaces and signals. Standardized FireWire cables and connectors replace the many disparate connections between consumer electronics devices and PCs. Different types of digital signals are multiplexed into one bus. Unlike Ethernet networks, real-time, high-speed data streams over FireWire do not require additional protocols. In addition, there are arbitration facilities that guarantee access to the bus in a given time. The use of bridges in FireWire networks allows you to isolate the traffic of groups of nodes from each other. 7.3. ACCESS.Bus and PC interface serial bus ACCESS.Bus (Accessory Bus), developed by DEC, is a bus for the interaction of a computer with its accessories, for example, a monitor (VESA DDC channel), smart power supplies (Smart Battery), etc. The bus allows two signal and two power supplies (12 V, 500 mA) wires connect up to 14 I/O devices, the bus length can reach 8 m. The hardware basis is the PC interface, which is characterized by ease of implementation, but even compared to USB, low performance. Above the PC hardware protocol for the ACCESS.Bus there is a basic software protocol with which the protocols of the specific connected devices interact. Protocols provide connection / disconnection of devices without rebooting the OS. The purpose of the signals of the ACCESS.Bus connector, proposed by VESA, is given in Table. 7.3.
Interface TO, developed by Philips, has recently appeared in the PC and is used as an internal auxiliary bus of the system board for communicating with the non-volatile identification memory of installed components (memory DIMMs). The bus is extremely easy to implement two signal lines that work with software. For its intended purpose, this bus is currently used only by the BIOS when determining hardware, but the use of writable configuration memory opens up new opportunities for linking software to a specific system (more precisely, an installed module) and ... for viruses. The method of software access to the bus has not yet been standardized, but if desired, it can be "calculated" by studying the documentation for the chipset.
Serial interface CSS provides bidirectional data transfer between a pair of devices using two signals: SDA (Serial Data) data and SCL (Serial Clock) clock. Two devices are involved in the exchange leading (Master) и slave. Each of them can act as transmitter, placing information bits on the SDA line, or receiver. The exchange protocol is illustrated in fig. 7.12. Synchronization is set by the master controller. The bidirectional data line with an "open collector" output is controlled by both devices in turn. The exchange frequency (not necessarily constant) is limited from above by 100 kHz for the standard mode and 400 kHz for the high-speed mode, which allows organizing a software-controlled implementation of the interface controller. Start of any operation condition Home triggered by a high-to-low transition of the SDA signal when SCL is high. The operation is completed by transferring the SDA signal from a low level to a high level with a high SCL condition Stop. When transmitting data, the state of the SDA line can only change when the SCL is low, the data bits are strobed with a positive SCL edge. Each frame consists of 8 data bits generated by the transmitter (the most significant bit of the MSB is transmitted first), after which the transmitter releases the data line for one cycle to receive an acknowledgment . The receiver during the ninth cycle forms a zero Ack confirmation bit. After the acknowledgment bit has been transmitted, the receiver can delay the next transmission by holding the SCL line low. The receiver can also slow down the bus at the receive level of each bit by keeping SCL low after its roll-off generated by the transmitter. Each slave has its own address, which defaults to 7 bits. Address A[6:0] transmitted by the master in bits [7:1] of the first byte, bit 0 contains the sign of the operation R1U(R1/U=1 read, RW=Q -record). A 7-bit address contains two parts: the upper 4 bits A[6:3] carry information about the device type (for example, for EEPROM 1010), and the lower 3 bits A[0:2] define the number of the device of this type. Many microcircuits with a PC interface have three address inputs, by switching them to logic levels 1 and 0, the required address is set. Some full address values are reserved (Table 7.4). All-call allows a wake-up device to announce itself in a broadcast manner. Byte Home is designed to draw the attention of the processor to the interface, if it is organized in the device in software (not hardware) way. Until this byte is received, the microcontroller of the device does not poll the status and does not monitor the interface signals. When using 10-bit addressing, bits [2:1] contain the high part of the address, and the low 8 bits will be transferred in the next byte if the sign RW=0. The address of the slave device and the type of call are set by the controller when the exchange is initiated. The memory exchange is illustrated in Fig. 7.13. Here SA[0:2] device address, DA[0:7] data address, D[0:7] data, W write flag (0), R read flag (1).
Having fulfilled the condition Start, the controller sends a byte containing the device address and the indication of the operation rw, and awaiting confirmation. At write operations the next message from the controller will be the 8-bit address of the cell being written, followed by a data byte (for microcircuits with a memory capacity of more than 256 bytes, the cell address is sent in two bytes). Having received confirmation, the controller ends the loop with the condition stop, and the addressed device may begin its internal write cycle during which it does not respond to interface signals. The controller checks if the device is ready by sending a write command (device address byte) and parsing the confirmation bit, then forming the condition Stop. If the device responds with an acknowledgment bit, then it has completed its internal loop and is ready for the next operation. Read operation is initiated in the same way as a record, but with the attribute RW=\. It is possible to read at a given address, at the current address, or sequentially. The current address is stored in the internal counter of the slave device, it contains the address of the cell involved in the last operation increased by one. Upon receiving a read command, the device gives an acknowledge bit and sends a data byte corresponding to the current address. The controller can respond with an acknowledgment, then the device will send the next byte (serial read). If the controller responds to the received data byte with the condition stop, the read operation ends (the case of reading at the current address). The controller sets the starting address for reading with a dummy write operation, in which the device address byte and the cell address byte are transmitted, and after receiving the address byte, the condition is formed again Home and the device address is transmitted, but with an indication of the read operation. This is how the reading of an arbitrary cell (or sequence of cells) is implemented. The interface allows the controller to use a pair of signals to access any of the 8 devices of the same type connected to this bus and having a unique address (Fig. 7.14). If you need to increase the number of devices, you can connect groups. In this case, it is possible to use both a common SCL signal and separate SDA signals (bidirectional), as well as a common SDA signal and separate unidirectional SCL signals. To access one of several microcircuits (or devices) that do not have pins for setting their own address, SCL (or SDA) line separation is also used. The PC protocol allows multiple controllers to share the same bus by detecting collisions and arbitrating. These functions are implemented quite simply: if two transmitters try to set different logical signal levels on the SDA lines, then the one that sets the low level will "win". The transmitter monitors the levels of the signals controlled by it and, if a discrepancy is detected (transmits a high level, but “sees” a low one), refuses further transmission. The device can initiate the exchange only in the passive state of the signals. Collision can occur only when trying to start an exchange at the same time, as soon as a conflict is detected, the "losing" transmitter will turn off, and the "winning" one will continue to work.
Appendix A. Systems engineering of IBM PC-compatible computers Here the interaction of programs with interface adapters is considered. Brief information on the PC architecture is given. The organization of memory and I/O spaces, the interrupt system, and direct memory access are described. More detailed information can be found in the book "Hardware IBM PC. Encyclopedia" ("Peter", 1998). A.1. memory space The logical structure of PC memory is determined by the addressing system of x86 family processors. The 8086/88 processors used in the early IBM PCs had a 1 MB address space (20 bits of the address bus). Starting with the 80286 processor, the address bus was extended to 24 bits, then (386DX, 486, Pentium) to 32, and finally to 36 bits (Pentium Pro, Pentium II). In the real processor mode used in DOS, only 1 MB of memory is formally available. However, due to an 8086 processor emulation bug in real mode, 80286 and higher processors have the maximum available address lOFFEFh, which is (64K-16) bytes more. The area lOOOOOh-lOFFEFh is called High Memory Area (HMA). Part of the real-mode OS and small resident programs are placed in it. For full compatibility with the 8086/88 processor, there is an address bus gate A20 GateA20, which either passes the signal from the processor, or forcibly resets the line A20 of the address system bus. Publication: cxem.net
Artificial leather for touch emulation
15.04.2024 Petgugu Global cat litter
15.04.2024 The attractiveness of caring men
14.04.2024
▪ Not stress is dangerous, but the reaction to it ▪ Charging gadgets with hot water ▪ Monitor Philips 275P4VYKEB 5120x2880 pixels
▪ section of the site Intercoms. Article selection ▪ Telescope article. History of invention and production ▪ article What is a quarry? Detailed answer ▪ article Plantain lanceolate. Legends, cultivation, methods of application
Home page | Library | Articles | Website map | Site Reviews
www.diagram.com.ua |
See other articles Section 
Latest news of science and technology, new electronics:
All languages of this page